Skip to content

V
VME64x core
Commit 5e23c326 authored by dpedrett's avatar dpedrett
Browse files
Options

Retry cycle termination supported. The WB32or64 register now is called WB32bits; less confusing 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@162 665b4545-5c6b-4c24-801b-41150b02b44b
parent 9e85a1ee
Hide whitespace changes
Inline Side-by-side
Showing with 22 additions and 21 deletions
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 5e23c326
...@@ -207,7 +207,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o ...@@ -207,7 +207,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
if reset = '1' then if reset = '1' then
s_CSRarray(BAR) <= (others => '0'); s_CSRarray(BAR) <= (others => '0');
s_bar_written <= '0'; s_bar_written <= '0';
for i in 254 downto WB32or64 loop -- Initialization of the CSR memory for i in 254 downto WB32bits loop -- Initialization of the CSR memory
s_CSRarray(i) <= c_csr_array(i); s_CSRarray(i) <= c_csr_array(i);
end loop; end loop;
elsif s_bar_written = '0' and s_odd_parity = '1' then elsif s_bar_written = '0' and s_odd_parity = '1' then
...@@ -270,19 +270,16 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o ...@@ -270,19 +270,16 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
s_CSRarray(IRQ_level) <= s_locDataIn(7 downto 0); s_CSRarray(IRQ_level) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_MBLT_Endian_addr(18 downto 2)) => when to_integer("00" & c_MBLT_Endian_addr(18 downto 2)) =>
s_CSRarray(MBLT_Endian) <= s_locDataIn(7 downto 0); s_CSRarray(MBLT_Endian) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_WB32or64_addr(18 downto 2)) =>
s_CSRarray(WB32or64) <= s_locDataIn(7 downto 0);
when others => null; when others => null;
end case; end case;
else else
if c_width = 32 then if c_width = 32 then
s_CSRarray(WB32or64) <= x"01"; s_CSRarray(WB32bits) <= x"01";
else else
s_CSRarray(WB32or64) <= x"00"; s_CSRarray(WB32bits) <= x"00";
end if; end if;
reset_flag <= '0'; reset_flag <= '0';
s_CSRarray(BYTES0) <= unsigned(numBytes(7 downto 0)); s_CSRarray(BYTES0) <= unsigned(numBytes(7 downto 0));
...@@ -352,7 +349,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o ...@@ -352,7 +349,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
when "00" & c_TIME4_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME4_ns); when "00" & c_TIME4_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME4_ns);
when "00" & c_BYTES0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES0); when "00" & c_BYTES0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES0);
when "00" & c_BYTES1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES1); when "00" & c_BYTES1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES1);
when "00" & c_WB32or64_addr(18 downto 2) => s_CSRdata <= s_CSRarray(WB32or64); when "00" & c_WB32bits_addr(18 downto 2) => s_CSRdata <= s_CSRarray(WB32bits);
when others => s_CSRdata <= (others => '0'); when others => s_CSRdata <= (others => '0');
end case; end case;
...@@ -380,7 +377,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o ...@@ -380,7 +377,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
ModuleEnable <= s_CSRarray(BIT_SET_CLR_REG)(4); ModuleEnable <= s_CSRarray(BIT_SET_CLR_REG)(4);
MBLT_Endian_o <= std_logic_vector(s_CSRarray(MBLT_Endian)(2 downto 0)); MBLT_Endian_o <= std_logic_vector(s_CSRarray(MBLT_Endian)(2 downto 0));
Sw_Reset <= s_CSRarray(BIT_SET_CLR_REG)(7); Sw_Reset <= s_CSRarray(BIT_SET_CLR_REG)(7);
W32 <= s_CSRarray(WB32or64)(0); W32 <= s_CSRarray(WB32bits)(0);
BAR_o <= s_BAR_o; BAR_o <= s_BAR_o;
s_BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3)); s_BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3));
--------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ 5e23c326
...@@ -149,7 +149,7 @@ package VME_CR_pack is ...@@ -149,7 +149,7 @@ package VME_CR_pack is
16#15# => x"00", 16#15# => x"00",
16#16# => x"00", 16#16# => x"00",
--Program Id code --Program Id code
16#1F# => x"54", 16#1F# => x"55",
--Offset to BEG_USER_CR --Offset to BEG_USER_CR
16#20# => x"00", 16#20# => x"00",
16#21# => x"00", 16#21# => x"00",
......
hdl/vme64x-core/rtl/VME_CSR_pack.vhd
View file @ 5e23c326
...@@ -78,7 +78,7 @@ FUNC6_ADER_3 =>x"00", ...@@ -78,7 +78,7 @@ FUNC6_ADER_3 =>x"00",
IRQ_Vector =>x"00", --"00" because each Slot has a different IRQ Vector IRQ_Vector =>x"00", --"00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value -- and the VME Master should set this value
IRQ_level =>x"02", IRQ_level =>x"02",
WB32or64 =>x"00", -- 32 bit WB of default WB32bits =>x"01", -- 32 bit WB of default
others => (others => '0')); others => (others => '0'));
end VME_CSR_pack; end VME_CSR_pack;
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ 5e23c326
...@@ -319,7 +319,7 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length)); ...@@ -319,7 +319,7 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
err <= err_i; err <= err_i;
rty <= rty_i; rty <= rty_i;
memAckWb <= memAckWB_i or s_AckWithError; memAckWb <= memAckWB_i or s_AckWithError or rty_i;
psize_o <= beatCount; psize_o <= beatCount;
end Behavioral; end Behavioral;
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 5e23c326
...@@ -222,7 +222,8 @@ architecture RTL of VME_bus is ...@@ -222,7 +222,8 @@ architecture RTL of VME_bus is
signal s_mainFSMreset : std_logic; -- Resets main FSM on AS r. edge signal s_mainFSMreset : std_logic; -- Resets main FSM on AS r. edge
signal s_dataPhase : std_logic; -- for A64 and multipl. transf. signal s_dataPhase : std_logic; -- for A64 and multipl. transf.
signal s_transferActive : std_logic; -- active VME transfer signal s_transferActive : std_logic; -- active VME transfer
signal s_retry : std_logic; -- RETRY signal -- signal s_retry : std_logic; -- RETRY signal
signal s_retry_out : std_logic;
signal s_berr : std_logic; -- BERR signal signal s_berr : std_logic; -- BERR signal
signal s_berr_1 : std_logic; -- signal s_berr_1 : std_logic; --
signal s_berr_2 : std_logic; -- signal s_berr_2 : std_logic; --
...@@ -532,7 +533,7 @@ begin ...@@ -532,7 +533,7 @@ begin
s_dataToAddrBus <= s_FSM.s_dataToAddrBus; s_dataToAddrBus <= s_FSM.s_dataToAddrBus;
s_transferActive <= s_FSM.s_transferActive; s_transferActive <= s_FSM.s_transferActive;
s_2eLatchAddr <= s_FSM.s_2eLatchAddr; s_2eLatchAddr <= s_FSM.s_2eLatchAddr;
s_retry <= s_FSM.s_retry; s_retry_out <= s_FSM.s_retry;
s_berr <= s_FSM.s_berr; s_berr <= s_FSM.s_berr;
s_BERR_out <= s_FSM.s_BERR_out; s_BERR_out <= s_FSM.s_BERR_out;
...@@ -666,9 +667,12 @@ begin ...@@ -666,9 +667,12 @@ begin
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i; s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase; s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1'; s_FSM.s_transferActive <= '1';
if s_BERRcondition = '0' then
if s_BERRcondition = '0' and s_rty1 = '0' then
s_FSM.s_mainDTACK <= '0'; s_FSM.s_mainDTACK <= '0';
else elsif s_BERRcondition = '0' and s_rty1 = '1' then
s_FSM.s_retry <= '1';
else
s_FSM.s_BERR_out <= '1'; s_FSM.s_BERR_out <= '1';
end if; end if;
...@@ -1000,7 +1004,7 @@ begin ...@@ -1000,7 +1004,7 @@ begin
p_RETRYdriver: process(clk_i) p_RETRYdriver: process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if s_rty1='1' or s_retry ='1' then if s_retry_out = '1' then
VME_RETRY_n_o <= '0'; VME_RETRY_n_o <= '0';
VME_RETRY_OE_o <= '1'; VME_RETRY_OE_o <= '1';
else else
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 5e23c326
...@@ -61,7 +61,7 @@ package vme64x_pack is ...@@ -61,7 +61,7 @@ package vme64x_pack is
--_______________________________________________________________________________ --_______________________________________________________________________________
-- Constants: -- Constants:
--WB data width: --WB data width:
constant c_width : integer := 64; --must be 32 or 64! constant c_width : integer := 32; --must be 32 or 64!
--CRAM size in the CR/CSR space (bytes): --CRAM size in the CR/CSR space (bytes):
constant c_CRAM_SIZE : integer := 1024; constant c_CRAM_SIZE : integer := 1024;
-- remember to set properly the "END_CRAM" register in the CR space -- remember to set properly the "END_CRAM" register in the CR space
...@@ -146,7 +146,7 @@ package vme64x_pack is ...@@ -146,7 +146,7 @@ package vme64x_pack is
constant TIME4_ns : integer := FUNC0_ADER_3 -9; constant TIME4_ns : integer := FUNC0_ADER_3 -9;
constant BYTES0 : integer := FUNC0_ADER_3 -10; constant BYTES0 : integer := FUNC0_ADER_3 -10;
constant BYTES1 : integer := FUNC0_ADER_3 -11; constant BYTES1 : integer := FUNC0_ADER_3 -11;
constant WB32or64 : integer := FUNC0_ADER_3 -12; constant WB32bits : integer := FUNC0_ADER_3 -12;
constant MBLT_Endian : integer := FUNC0_ADER_3 -4; constant MBLT_Endian : integer := FUNC0_ADER_3 -4;
-- Initialization CR: -- Initialization CR:
...@@ -249,7 +249,7 @@ package vme64x_pack is ...@@ -249,7 +249,7 @@ package vme64x_pack is
constant c_TIME4_ns_addr : unsigned(19 downto 0) := x"7FF3f"; constant c_TIME4_ns_addr : unsigned(19 downto 0) := x"7FF3f";
constant c_BYTES0_addr : unsigned(19 downto 0) := x"7FF3b"; constant c_BYTES0_addr : unsigned(19 downto 0) := x"7FF3b";
constant c_BYTES1_addr : unsigned(19 downto 0) := x"7FF37"; constant c_BYTES1_addr : unsigned(19 downto 0) := x"7FF37";
constant c_WB32or64_addr : unsigned(19 downto 0) := x"7FF33"; constant c_WB32bits_addr : unsigned(19 downto 0) := x"7FF33";
constant c_MBLT_Endian_addr : unsigned(19 downto 0) := x"7FF53"; -- VME64x reserved CSR constant c_MBLT_Endian_addr : unsigned(19 downto 0) := x"7FF53"; -- VME64x reserved CSR
--___________________________________________________________________________________________ --___________________________________________________________________________________________
...@@ -353,7 +353,7 @@ package vme64x_pack is ...@@ -353,7 +353,7 @@ package vme64x_pack is
type t_FUNC_32b_array_std is array (0 to 7) of std_logic_vector(31 downto 0); -- ADER register array type t_FUNC_32b_array_std is array (0 to 7) of std_logic_vector(31 downto 0); -- ADER register array
type t_FUNC_64b_array_std is array (0 to 7) of std_logic_vector(63 downto 0); -- AMCAP register array type t_FUNC_64b_array_std is array (0 to 7) of std_logic_vector(63 downto 0); -- AMCAP register array
type t_FUNC_256b_array_std is array (0 to 7) of std_logic_vector(255 downto 0); -- XAMCAP register array type t_FUNC_256b_array_std is array (0 to 7) of std_logic_vector(255 downto 0); -- XAMCAP register array
type t_CSRarray is array(BAR downto WB32or64) of unsigned(7 downto 0); type t_CSRarray is array(BAR downto WB32bits) of unsigned(7 downto 0);
type t_cr_array is array (natural range <>) of std_logic_vector(7 downto 0); type t_cr_array is array (natural range <>) of std_logic_vector(7 downto 0);
-- functions -- functions
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment