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VME64x core
Commit 6d88bf97 authored by Tom Levens's avatar Tom Levens
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Add generics to configure CR space 

Generics have been added to configure all values (ADEM, AMCAP, XAMCAP,
DAWPR, etc) in the CR space. This implements Feature #767 and #791 and
invalidates Bug #1403.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 7a8f2b5c
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Showing with 898 additions and 866 deletions
hdl/vme64x-core/rtl/Manifest.py
View file @ 6d88bf97
......@@ -6,8 +6,6 @@ files = [ "xvme64x_core.vhd",
"VME_Am_Match.vhd",
"VME_bus.vhd",
"VME_CR_CSR_Space.vhd",
"VME_CR_pack.vhd",
"VME_CSR_pack.vhd",
"VME_CRAM.vhd",
"VME_Funct_Match.vhd",
"VME_Init.vhd",
......
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 6d88bf97
......@@ -108,7 +108,6 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
entity VME64xCore_Top is
generic (
......@@ -116,22 +115,16 @@ entity VME64xCore_Top is
g_wb_data_width : integer := c_width; -- WB data width: must be 32 or 64
g_wb_addr_width : integer := c_addr_width; -- WB address width: 64 or less
---------------------------------------------------------------------------
-- CR/CSR
---------------------------------------------------------------------------
-- CRAM
g_CRAM_Size : integer := c_CRAM_SIZE;
-- Manufacturer ID: IEEE OUID
-- e.g. CERN is 0x080030
g_ManufacturerID : integer := c_CERN_ID;
g_manufacturer_id : std_logic_vector(23 downto 0) := x"000000";
-- Board ID: Per manufacturer, each board shall have an unique ID
-- e.g. SVEC = 408 (CERN IDs: http://cern.ch/boardid)
g_BoardID : integer := c_SVEC_ID;
g_board_id : std_logic_vector(31 downto 0) := x"00000000";
-- Revision ID: user defined revision code
g_RevisionID : integer := c_RevisionID;
g_revision_id : std_logic_vector(31 downto 0) := x"00000000";
-- Program ID: Defined per AV1:
-- 0x00 = Not used
......@@ -141,12 +134,71 @@ entity VME64xCore_Top is
-- 0x80-0xEF = Reserved for future use
-- 0xF0-0xFE = Reserved for Boot Firmware (P1275)
-- 0xFF = Not to be used
g_ProgramID : integer := 90;
-- The default values can be found in the vme64x_pack;
g_adem_a24 : std_logic_vector(31 downto 0) := x"ff800000";
g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
g_program_id : std_logic_vector(7 downto 0) := x"00";
-- Pointer to a user defined ASCII string
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
-- User CR/CSR, CRAM & serial number pointers
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001000";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
-- Function 0
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 1
g_f1_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 2
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 3
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 4
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 5
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 6
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 7
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -213,23 +265,8 @@ end VME64xCore_Top;
architecture RTL of VME64xCore_Top is
impure function f_setup_window_sizes(cr : t_cr_array) return t_cr_array is
variable tmp : t_cr_array(2**12 downto 0);
begin
tmp := cr;
tmp(16#188#) := g_adem_a32(31 downto 24);
tmp(16#189#) := g_adem_a32(23 downto 16);
tmp(16#18A#) := g_adem_a32(15 downto 8);
tmp(16#18B#) := g_adem_a32(7 downto 0);
tmp(16#18c#) := g_adem_a24(31 downto 24);
tmp(16#18d#) := g_adem_a24(23 downto 16);
tmp(16#18e#) := g_adem_a24(15 downto 8);
tmp(16#18f#) := g_adem_a24(7 downto 0);
return tmp;
end function;
signal s_CRAMdataOut : std_logic_vector(7 downto 0);
signal s_CRAMaddr : std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
signal s_CRAMaddr : std_logic_vector(f_log2_size(f_size(g_beg_cram, g_end_cram))-1 downto 0);
signal s_CRAMdataIn : std_logic_vector(7 downto 0);
signal s_CRAMwea : std_logic;
signal s_CRaddr : std_logic_vector(11 downto 0);
......@@ -308,7 +345,7 @@ begin
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_cram_size => g_cram_size
g_cram_size => f_size(g_beg_cram, g_end_cram)
)
port map (
clk_i => clk_i,
......@@ -436,13 +473,24 @@ begin
------------------------------------------------------------------------------
Inst_VME_CR_CSR_Space : VME_CR_CSR_Space
generic map (
g_cram_size => g_cram_size,
g_cram_size => f_size(g_beg_cram, g_end_cram),
g_wb_data_width => g_wb_data_width,
g_CRspace => f_setup_window_sizes(c_cr_array),
g_BoardID => g_BoardID,
g_ManufacturerID => g_ManufacturerID,
g_RevisionID => g_RevisionID,
g_ProgramID => g_ProgramID
g_cr_space => f_vme_cr_encode(
g_manufacturer_id, g_board_id, g_revision_id, g_program_id,
g_ascii_ptr,
g_beg_user_cr, g_end_user_cr,
g_beg_cram, g_end_cram,
g_beg_user_csr, g_end_user_csr,
g_beg_sn, g_end_sn,
g_f0_adem, g_f0_amcap, g_f0_xamcap, g_f0_dawpr,
g_f1_adem, g_f1_amcap, g_f1_xamcap, g_f1_dawpr,
g_f2_adem, g_f2_amcap, g_f2_xamcap, g_f2_dawpr,
g_f3_adem, g_f3_amcap, g_f3_xamcap, g_f3_dawpr,
g_f4_adem, g_f4_amcap, g_f4_xamcap, g_f4_dawpr,
g_f5_adem, g_f5_amcap, g_f5_xamcap, g_f5_dawpr,
g_f6_adem, g_f6_amcap, g_f6_xamcap, g_f6_dawpr,
g_f7_adem, g_f7_amcap, g_f7_xamcap, g_f7_dawpr
)
)
port map (
clk_i => clk_i,
......
hdl/vme64x-core/rtl/VME_CRAM.vhd
View file @ 6d88bf97
......@@ -39,7 +39,7 @@ use work.vme64x_pack.all;
entity VME_CRAM is
generic (
dl : integer;
al : integer := f_log2_size(c_CRAM_SIZE)
al : integer
);
port (
clk : in std_logic;
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 6d88bf97
......@@ -136,18 +136,12 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
entity VME_CR_CSR_Space is
generic (
g_cram_size : integer := c_CRAM_SIZE;
g_wb_data_width : integer := c_width;
g_CRspace : t_cr_array := c_cr_array;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96 -- 0x00000060
g_cram_size : integer;
g_wb_data_width : integer;
g_cr_space : t_cr_array
);
port (
-- VMEbus.vhd signals
......@@ -189,11 +183,10 @@ end VME_CR_CSR_Space;
architecture Behavioral of VME_CR_CSR_Space is
signal s_CSRarray : t_CSRarray; -- Array of CSR registers
signal s_CSRarray : t_csr_array; -- Array of CSR registers
signal s_bar_written : std_logic;
signal s_CSRdata : unsigned(7 downto 0);
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_CR_Space : t_cr_array(2**12 downto 0);
signal s_CrCsrOffsetAddr : unsigned(18 downto 0);
signal s_locDataIn : unsigned(7 downto 0);
signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
......@@ -213,13 +206,11 @@ begin
-- out error in the VME bus.
--s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
s_CR_Space <= f_set_CR_space(g_BoardID, g_CRspace, g_ManufacturerID, g_RevisionID, g_ProgramID);
-- CR
process(clk_i)
begin
if rising_edge(clk_i) then
CR_data <= s_CR_Space(to_integer(unsigned(CR_addr)));
CR_data <= g_cr_space(to_integer(unsigned(CR_addr)));
end if;
end process;
......@@ -236,8 +227,8 @@ begin
if reset = '1' then
s_CSRarray(BAR) <= (others => '0');
s_bar_written <= '0';
for i in 254 downto WB32bits loop -- Initialization of the CSR memory
s_CSRarray(i) <= c_csr_array(i);
for i in BAR-1 downto WB32bits loop -- Initialization of the CSR memory
s_CSRarray(i) <= x"00";
end loop;
elsif s_bar_written = '0' and s_odd_parity = '1' then
-- initialization of BAR reg to access the CR/CSR space
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd deleted 100644 → 0
View file @ 7a8f2b5c
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_CR_pack (VME_CR_pack.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: ROM memory (CR space)
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
package VME_CR_pack is
constant c_amcap : std_logic_vector(63 downto 0) :=
"1111111100000000001100100000000000000000000100001111111100001011";
constant c_amcap0 : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000001011101100000000"; -- A32
constant c_amcapMBLT : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000100000000";
constant c_amcap1 : std_logic_vector(63 downto 0) :=
"1011101100000000000000000000000000000000000000000000000000000000"; -- A24
constant c_amcap2 : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000000000000"; -- disabled
constant c_amcapA64 : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000000000000"; -- disabled
constant c_amcap2e : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000000000000"; -- disabled
constant c_xamcap0 : std_logic_vector(255 downto 0) :=
(others => '0');
constant c_xamcap2 : std_logic_vector(255 downto 0) :=
x"0000000000000000000000000000000000000000000000000000000000060006";
constant c_amb : t_cr_array(0 to 7) := (
c_amcap(7 downto 0), c_amcap(15 downto 8),
c_amcap(23 downto 16), c_amcap(31 downto 24),
c_amcap(39 downto 32), c_amcap(47 downto 40),
c_amcap(55 downto 48), c_amcap(63 downto 56)
);
constant c_amb0 : t_cr_array(0 to 7) := (
c_amcap0(7 downto 0), c_amcap0(15 downto 8),
c_amcap0(23 downto 16), c_amcap0(31 downto 24),
c_amcap0(39 downto 32), c_amcap0(47 downto 40),
c_amcap0(55 downto 48), c_amcap0(63 downto 56)
);
constant c_amb1 : t_cr_array(0 to 7) := (
c_amcap1(7 downto 0), c_amcap1(15 downto 8),
c_amcap1(23 downto 16), c_amcap1(31 downto 24),
c_amcap1(39 downto 32), c_amcap1(47 downto 40),
c_amcap1(55 downto 48), c_amcap1(63 downto 56)
);
constant c_amb2 : t_cr_array(0 to 7) := (
c_amcap2(7 downto 0), c_amcap2(15 downto 8),
c_amcap2(23 downto 16), c_amcap2(31 downto 24),
c_amcap2(39 downto 32), c_amcap2(47 downto 40),
c_amcap2(55 downto 48), c_amcap2(63 downto 56)
);
constant c_amb2e : t_cr_array(0 to 7) := (
c_amcap2e(7 downto 0), c_amcap2e(15 downto 8),
c_amcap2e(23 downto 16), c_amcap2e(31 downto 24),
c_amcap2e(39 downto 32), c_amcap2e(47 downto 40),
c_amcap2e(55 downto 48), c_amcap2e(63 downto 56)
);
constant c_amb64 : t_cr_array(0 to 7) := (
c_amcapA64(7 downto 0), c_amcapA64(15 downto 8),
c_amcapA64(23 downto 16), c_amcapA64(31 downto 24),
c_amcapA64(39 downto 32), c_amcapA64(47 downto 40),
c_amcapA64(55 downto 48), c_amcapA64(63 downto 56)
);
constant c_xam0 : t_cr_array(0 to 31) := (
c_xamcap0(7 downto 0), c_xamcap0(15 downto 8), c_xamcap0(23 downto 16),
c_xamcap0(31 downto 24), c_xamcap0(39 downto 32), c_xamcap0(47 downto 40),
c_xamcap0(55 downto 48), c_xamcap0(63 downto 56), c_xamcap0(71 downto 64),
c_xamcap0(79 downto 72), c_xamcap0(87 downto 80), c_xamcap0(95 downto 88),
c_xamcap0(103 downto 96), c_xamcap0(111 downto 104), c_xamcap0(119 downto 112),
c_xamcap0(127 downto 120), c_xamcap0(135 downto 128), c_xamcap0(143 downto 136),
c_xamcap0(151 downto 144), c_xamcap0(159 downto 152), c_xamcap0(167 downto 160),
c_xamcap0(175 downto 168), c_xamcap0(183 downto 176), c_xamcap0(191 downto 184),
c_xamcap0(199 downto 192), c_xamcap0(207 downto 200), c_xamcap0(215 downto 208),
c_xamcap0(223 downto 216), c_xamcap0(231 downto 224), c_xamcap0(239 downto 232),
c_xamcap0(247 downto 240), c_xamcap0(255 downto 248)
);
constant c_xam2 : t_cr_array(0 to 31) := (
c_xamcap2(7 downto 0), c_xamcap2(15 downto 8), c_xamcap2(23 downto 16),
c_xamcap2(31 downto 24), c_xamcap2(39 downto 32), c_xamcap2(47 downto 40),
c_xamcap2(55 downto 48), c_xamcap2(63 downto 56), c_xamcap2(71 downto 64),
c_xamcap2(79 downto 72), c_xamcap2(87 downto 80), c_xamcap2(95 downto 88),
c_xamcap2(103 downto 96), c_xamcap2(111 downto 104), c_xamcap2(119 downto 112),
c_xamcap2(127 downto 120), c_xamcap2(135 downto 128), c_xamcap2(143 downto 136),
c_xamcap2(151 downto 144), c_xamcap2(159 downto 152), c_xamcap2(167 downto 160),
c_xamcap2(175 downto 168), c_xamcap2(183 downto 176), c_xamcap2(191 downto 184),
c_xamcap2(199 downto 192), c_xamcap2(207 downto 200), c_xamcap2(215 downto 208),
c_xamcap2(223 downto 216), c_xamcap2(231 downto 224), c_xamcap2(239 downto 232),
c_xamcap2(247 downto 240), c_xamcap2(255 downto 248)
);
constant c_cr_array : t_cr_array(2**12 downto 0) := (
16#00# => (others => '0'),
-- Length of ROM
16#01# => x"00",
16#02# => x"10",
16#03# => x"00",
-- Configuration ROM data acces width
16#04# => x"84", -- D32, D16, D08
-- CSR data acces width
16#05# => x"84", -- D32, D16, D08
-- CR/CSR Space Specification ID
16#06# => x"02", -- ASCII "C"
16#07# => x"43", -- ASCII "R"
16#08# => x"52",
-- Manufacturer's ID
16#09# => x"08", -- for CERN: 0x080030
16#0A# => x"00",
16#0B# => x"30",
-- Board ID
16#0C# => x"03", -- eg: SVEC ID = 0x000198
16#0D# => x"04",
16#0E# => x"04",
16#0F# => x"03",
-- Rev ID
16#10# => x"00",
16#11# => x"00",
16#12# => x"00",
16#13# => x"02",
-- Point to ASCII null terminatied
16#14# => x"00",
16#15# => x"00",
16#16# => x"00",
-- Program ID code
16#1F# => x"5a",
-- Offset to BEG_USER_CR
16#20# => x"00",
16#21# => x"00",
16#22# => x"00",
-- Offset to END_USER_CR
16#23# => x"00",
16#24# => x"00",
16#25# => x"00",
-- Offset to BEG_CRAM
16#26# => x"00",
16#27# => x"10",
16#28# => x"00",
-- Offset to END_CRAM
16#29# => x"00",
16#2A# => x"13",
16#2B# => x"ff",
-- Offset to BEG_USER_CSR
16#2C# => x"00",
16#2D# => x"00",
16#2E# => x"00", -- 0x7fbf0 and NOT 0x7fbf3 because is possible access with D32 mode
-- Offset to END_USER_CSR
16#2F# => x"00",
16#30# => x"00",
16#31# => x"00",
-- CRAM_ACCESS_WIDTH
16#3f# => x"84", -- D32, D16, D08
-- DAWPR
16#40# => x"84", -- Fun 0 accepts D64, D32, D16, D08(EO) cycles
16#41# => x"84", -- Fun 1
16#42# => x"84", -- Fun 2
16#43# => x"84", -- Fun 3
16#44# => x"84", -- Fun 4
16#45# => x"84", -- Fun 5
16#46# => x"84", -- Fun 6
16#47# => x"84", -- Fun 7
-- AMCAP
16#48# => c_amb0(7), -- Fun 0 for A32 S, A32 BLT, A32 MBLT
16#49# => c_amb0(6), -- Fun 0
16#4A# => c_amb0(5), -- Fun 0
16#4B# => c_amb0(4), -- Fun 0
16#4C# => c_amb0(3), -- Fun 0
16#4D# => c_amb0(2), -- Fun 0
16#4E# => c_amb0(1), -- Fun 0
16#4F# => c_amb0(0), -- Fun 0
16#50# => c_amb1(7), -- Fun 1 for A24 S, A24 BLT, A24 MBLT
16#51# => c_amb1(6), -- Fun 1
16#52# => c_amb1(5), -- Fun 1
16#53# => c_amb1(4), -- Fun 1
16#54# => c_amb1(3), -- Fun 1
16#55# => c_amb1(2), -- Fun 1
16#56# => c_amb1(1), -- Fun 1
16#57# => c_amb1(0), -- Fun 1
16#58# => c_amb2(7), -- Fun 2 for A16
16#59# => c_amb2(6), -- Fun 2
16#5A# => c_amb2(5), -- Fun 2
16#5B# => c_amb2(4), -- Fun 2
16#5C# => c_amb2(3), -- Fun 2
16#5D# => c_amb2(2), -- Fun 2
16#5E# => c_amb2(1), -- Fun 2
16#5F# => c_amb2(0), -- Fun 2
16#60# => c_amb64(7), -- Fun 3 for A64 S, A64 BLT, A64 MBLT
16#61# => c_amb64(6), -- Fun 3
16#62# => c_amb64(5), -- Fun 3
16#63# => c_amb64(4), -- Fun 3
16#64# => c_amb64(3), -- Fun 3
16#65# => c_amb64(2), -- Fun 3
16#66# => c_amb64(1), -- Fun 3
16#67# => c_amb64(0), -- Fun 3
16#68# => x"00", -- Fun 3_b These are not used because the FUNC 3 decode
16#69# => x"00", -- Fun 3_b the access mode: A64 --> 2 ADER, 2 ADEM
16#6A# => x"00", -- Fun 3_b
16#6B# => x"00", -- Fun 3_b
16#6C# => x"00", -- Fun 3_b
16#6D# => x"00", -- Fun 3_b
16#6E# => x"00", -- Fun 3_b
16#6F# => x"00", -- Fun 3_b
16#70# => c_amb2e(7), -- Fun 4
16#71# => c_amb2e(6), -- Fun 4
16#72# => c_amb2e(5), -- Fun 4
16#73# => c_amb2e(4), -- Fun 4
16#74# => c_amb2e(3), -- Fun 4
16#75# => c_amb2e(2), -- Fun 4
16#76# => c_amb2e(1), -- Fun 4
16#77# => c_amb2e(0), -- Fun 4
16#78# => x"00", -- Fun 4_b
16#79# => x"00", -- Fun 4_b
16#7A# => x"00", -- Fun 4_b
16#7B# => x"00", -- Fun 4_b
16#7C# => x"00", -- Fun 4_b
16#7D# => x"00", -- Fun 4_b
16#7E# => x"00", -- Fun 4_b
16#7F# => x"00", -- Fun 4_b
-- XAMCAP
16#88# => c_xam0(31), -- Fun 0 XAMCAP MSB
16#89# => c_xam0(30),
16#8A# => c_xam0(29),
16#8B# => c_xam0(28),
16#8C# => c_xam0(27),
16#8D# => c_xam0(26),
16#8E# => c_xam0(25),
16#8F# => c_xam0(24),
16#90# => c_xam0(23),
16#91# => c_xam0(22),
16#92# => c_xam0(21),
16#93# => c_xam0(20),
16#94# => c_xam0(19),
16#95# => c_xam0(18),
16#96# => c_xam0(17),
16#97# => c_xam0(16),
16#98# => c_xam0(15),
16#99# => c_xam0(14),
16#9A# => c_xam0(13),
16#9B# => c_xam0(12),
16#9C# => c_xam0(11),
16#9D# => c_xam0(10),
16#9E# => c_xam0(9),
16#9F# => c_xam0(8),
16#A0# => c_xam0(7),
16#A1# => c_xam0(6),
16#A2# => c_xam0(5),
16#A3# => c_xam0(4),
16#A4# => c_xam0(3),
16#A5# => c_xam0(2),
16#A6# => c_xam0(1),
16#A7# => c_xam0(0),
16#A8# => c_xam0(31), -- Fun 1 XAMCAP MSB
16#A9# => c_xam0(30),
16#AA# => c_xam0(29),
16#AB# => c_xam0(28),
16#AC# => c_xam0(27),
16#AD# => c_xam0(26),
16#AE# => c_xam0(25),
16#AF# => c_xam0(24),
16#B0# => c_xam0(23),
16#B1# => c_xam0(22),
16#B2# => c_xam0(21),
16#B3# => c_xam0(20),
16#B4# => c_xam0(19),
16#B5# => c_xam0(18),
16#B6# => c_xam0(17),
16#B7# => c_xam0(16),
16#B8# => c_xam0(15),
16#B9# => c_xam0(14),
16#BA# => c_xam0(13),
16#BB# => c_xam0(12),
16#BC# => c_xam0(11),
16#BD# => c_xam0(10),
16#BE# => c_xam0(9),
16#BF# => c_xam0(8),
16#C0# => c_xam0(7),
16#C1# => c_xam0(6),
16#C2# => c_xam0(5),
16#C3# => c_xam0(4),
16#C4# => c_xam0(3),
16#C5# => c_xam0(2),
16#C6# => c_xam0(1),
16#C7# => c_xam0(0),
16#C8# => c_xam0(31), -- Fun 2 XAMCAP MSB
16#C9# => c_xam0(30),
16#CA# => c_xam0(29),
16#CB# => c_xam0(28),
16#CC# => c_xam0(27),
16#CD# => c_xam0(26),
16#CE# => c_xam0(25),
16#CF# => c_xam0(24),
16#D0# => c_xam0(23),
16#D1# => c_xam0(22),
16#D2# => c_xam0(21),
16#D3# => c_xam0(20),
16#D4# => c_xam0(19),
16#D5# => c_xam0(18),
16#D6# => c_xam0(17),
16#D7# => c_xam0(16),
16#D8# => c_xam0(15),
16#D9# => c_xam0(14),
16#DA# => c_xam0(13),
16#DB# => c_xam0(12),
16#DC# => c_xam0(11),
16#DD# => c_xam0(10),
16#DE# => c_xam0(9),
16#DF# => c_xam0(8),
16#E0# => c_xam0(7),
16#E1# => c_xam0(6),
16#E2# => c_xam0(5),
16#E3# => c_xam0(4),
16#E4# => c_xam0(3),
16#E5# => c_xam0(2),
16#E6# => c_xam0(1),
16#E7# => c_xam0(0),
16#E8# => c_xam0(31), -- Fun 3 XAMCAP MSB
16#E9# => c_xam0(30),
16#EA# => c_xam0(29),
16#EB# => c_xam0(28),
16#EC# => c_xam0(27),
16#ED# => c_xam0(26),
16#EE# => c_xam0(25),
16#EF# => c_xam0(24),
16#F0# => c_xam0(23),
16#F1# => c_xam0(22),
16#F2# => c_xam0(21),
16#F3# => c_xam0(20),
16#F4# => c_xam0(19),
16#F5# => c_xam0(18),
16#F6# => c_xam0(17),
16#F7# => c_xam0(16),
16#F8# => c_xam0(15),
16#F9# => c_xam0(14),
16#FA# => c_xam0(13),
16#FB# => c_xam0(12),
16#FC# => c_xam0(11),
16#FD# => c_xam0(10),
16#FE# => c_xam0(9),
16#FF# => c_xam0(8),
16#100# => c_xam0(7),
16#101# => c_xam0(6),
16#102# => c_xam0(5),
16#103# => c_xam0(4),
16#104# => c_xam0(3),
16#105# => c_xam0(2),
16#106# => c_xam0(1),
16#107# => c_xam0(0),
16#108# => c_xam0(31), -- Fun 3_b XAMCAP MSB
16#109# => c_xam0(30),
16#10A# => c_xam0(29),
16#10B# => c_xam0(28),
16#10C# => c_xam0(27),
16#10D# => c_xam0(26),
16#10E# => c_xam0(25),
16#10F# => c_xam0(24),
16#110# => c_xam0(23),
16#111# => c_xam0(22),
16#112# => c_xam0(21),
16#113# => c_xam0(20),
16#114# => c_xam0(19),
16#115# => c_xam0(18),
16#116# => c_xam0(17),
16#117# => c_xam0(16),
16#118# => c_xam0(15),
16#119# => c_xam0(14),
16#11A# => c_xam0(13),
16#11B# => c_xam0(12),
16#11C# => c_xam0(11),
16#11D# => c_xam0(10),
16#11E# => c_xam0(9),
16#11F# => c_xam0(8),
16#120# => c_xam0(7),
16#121# => c_xam0(6),
16#122# => c_xam0(5),
16#123# => c_xam0(4),
16#124# => c_xam0(3),
16#125# => c_xam0(2),
16#126# => c_xam0(1),
16#127# => c_xam0(0),
16#128# => c_xam2(31), -- Fun 4 XAMCAP MSB
16#129# => c_xam2(30),
16#12A# => c_xam2(29),
16#12B# => c_xam2(28),
16#12C# => c_xam2(27),
16#12D# => c_xam2(26),
16#12E# => c_xam2(25),
16#12F# => c_xam2(24),
16#130# => c_xam2(23),
16#131# => c_xam2(22),
16#132# => c_xam2(21),
16#133# => c_xam2(20),
16#134# => c_xam2(19),
16#135# => c_xam2(18),
16#136# => c_xam2(17),
16#137# => c_xam2(16),
16#138# => c_xam2(15),
16#139# => c_xam2(14),
16#13A# => c_xam2(13),
16#13B# => c_xam2(12),
16#13C# => c_xam2(11),
16#13D# => c_xam2(10),
16#13E# => c_xam2(9),
16#13F# => c_xam2(8),
16#140# => c_xam2(7),
16#141# => c_xam2(6),
16#142# => c_xam2(5),
16#143# => c_xam2(4),
16#144# => c_xam2(3),
16#145# => c_xam2(2),
16#146# => c_xam2(1),
16#147# => c_xam2(0),
16#148# => c_xam0(31), -- Fun 4_b XAMCAP MSB
16#149# => c_xam0(30),
16#14A# => c_xam0(29),
16#14B# => c_xam0(28),
16#14C# => c_xam0(27),
16#14D# => c_xam0(26),
16#14E# => c_xam0(25),
16#14F# => c_xam0(24),
16#150# => c_xam0(23),
16#151# => c_xam0(22),
16#152# => c_xam0(21),
16#153# => c_xam0(20),
16#154# => c_xam0(19),
16#155# => c_xam0(18),
16#156# => c_xam0(17),
16#157# => c_xam0(16),
16#158# => c_xam0(15),
16#159# => c_xam0(14),
16#15A# => c_xam0(13),
16#15B# => c_xam0(12),
16#15C# => c_xam0(11),
16#15D# => c_xam0(10),
16#15E# => c_xam0(9),
16#15F# => c_xam0(8),
16#160# => c_xam0(7),
16#161# => c_xam0(6),
16#162# => c_xam0(5),
16#163# => c_xam0(4),
16#164# => c_xam0(3),
16#165# => c_xam0(2),
16#166# => c_xam0(1),
16#167# => c_xam0(0),
16#168# => c_xam0(31), -- Fun 5 XAMCAP MSB
16#169# => c_xam0(30),
16#16A# => c_xam0(29),
16#16B# => c_xam0(28),
16#16C# => c_xam0(27),
16#16D# => c_xam0(26),
16#16E# => c_xam0(25),
16#16F# => c_xam0(24),
16#170# => c_xam0(23),
16#171# => c_xam0(22),
16#172# => c_xam0(21),
16#173# => c_xam0(20),
16#174# => c_xam0(19),
16#175# => c_xam0(18),
16#176# => c_xam0(17),
16#177# => c_xam0(16),
16#178# => c_xam0(15),
16#179# => c_xam0(14),
16#17A# => c_xam0(13),
16#17B# => c_xam0(12),
16#17C# => c_xam0(11),
16#17D# => c_xam0(10),
16#17E# => c_xam0(9),
16#17F# => c_xam0(8),
16#180# => c_xam0(7),
16#181# => c_xam0(6),
16#182# => c_xam0(5),
16#183# => c_xam0(4),
16#184# => c_xam0(3),
16#185# => c_xam0(2),
16#186# => c_xam0(1),
16#187# => c_xam0(0),
-- ADEM
16#188# => x"ff", -- Fun 0
16#189# => x"00", -- Fun 0
16#18A# => x"00", -- Fun 0
16#18B# => x"00", -- Fun 0 --DFS = '0'
16#18c# => x"ff", -- Fun 1
16#18d# => x"f8", -- Fun 1
16#18e# => x"00", -- Fun 1
16#18f# => x"00", -- Fun 1 --DFS = '0'
16#190# => x"00", -- Fun 2
16#191# => x"00", -- Fun 2
16#192# => x"f0", -- Fun 2
16#193# => x"00", -- Fun 2 --DFS = '0'
16#194# => x"00", -- Fun 3
16#195# => x"00", -- Fun 3
16#196# => x"00", -- Fun 3
16#197# => x"01", -- Fun 3
16#198# => x"ff", -- Fun 4 (used for decoding FUNC3)
16#199# => x"00", -- Fun 4 (used for decoding FUNC3)
16#19a# => x"00", -- Fun 4 (used for decoding FUNC3)
16#19b# => x"00", -- Fun 4 (used for decoding FUNC3)
16#19c# => x"ff", -- Fun 5
16#19d# => x"00", -- Fun 5
16#19e# => x"00", -- Fun 5
16#19f# => x"01", -- Fun 5
16#1a0# => x"00", -- Fun 6
16#1a1# => x"00", -- Fun 6
16#1a2# => x"00", -- Fun 6
16#1a3# => x"00", -- Fun 6
others => (others => '0')
);
end VME_CR_pack;
hdl/vme64x-core/rtl/VME_CSR_pack.vhd deleted 100644 → 0
View file @ 7a8f2b5c
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_CSR_pack (VME_CSR_pack.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description: This file defines the default configuration of the CSR space
-- after power-up or software reset.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pack.all;
package VME_CSR_pack is
constant c_csr_array : t_CSRarray := (
BAR => x"00", -- CR/CSR BAR
BIT_SET_CLR_REG => x"00", -- Bit set register
-- 0x10 = module enable
USR_BIT_SET_CLR_REG => x"00", -- Bit clear register
CRAM_OWNER => x"00", -- CRAM_OWNER
FUNC0_ADER_0 => x"00", -- A32_S "24"
FUNC0_ADER_1 => x"00", -- "00"
FUNC0_ADER_2 => x"00", -- "00"
FUNC0_ADER_3 => x"00", -- "c0"
FUNC1_ADER_0 => x"00", -- A24_S "e4"
FUNC1_ADER_1 => x"00", -- "00"
FUNC1_ADER_2 => x"00", -- "c0"
FUNC1_ADER_3 => x"00", -- "00"
FUNC2_ADER_0 => x"00", -- A16_S "a4"
FUNC2_ADER_1 => x"00", -- "c0"
FUNC2_ADER_2 => x"00", -- "00"
FUNC2_ADER_3 => x"00", -- "00"
FUNC3_ADER_0 => x"00", -- A64_S "04"
FUNC3_ADER_1 => x"00",
FUNC3_ADER_2 => x"00",
FUNC3_ADER_3 => x"00",
FUNC4_ADER_0 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_1 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_2 => x"00", -- used for decoding the FUNC3
FUNC4_ADER_3 => x"00", -- used for decoding the FUNC3 "c0"
FUNC5_ADER_0 => x"00",
FUNC5_ADER_1 => x"00",
FUNC5_ADER_2 => x"00",
FUNC5_ADER_3 => x"00",
FUNC6_ADER_0 => x"00",
FUNC6_ADER_1 => x"00",
FUNC6_ADER_2 => x"00",
FUNC6_ADER_3 => x"00",
IRQ_Vector => x"00", -- "00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value
IRQ_level => x"02",
WB32bits => x"01", -- 32 bit WB of default
others => (others => '0')
);
end VME_CSR_pack;
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ 6d88bf97
......@@ -73,8 +73,8 @@ use work.vme64x_pack.all;
entity VME_Wb_master is
generic (
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
g_wb_data_width : integer;
g_wb_addr_width : integer
);
port (
memReq_i : in std_logic;
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 6d88bf97
......@@ -72,10 +72,10 @@ use work.vme64x_pack.all;
entity VME_bus is
generic (
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_cram_size : integer
);
port (
clk_i : in std_logic;
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 6d88bf97
......@@ -88,42 +88,20 @@ package vme64x_pack is
--WB data width:
constant c_width : integer := 64; -- must be 32 or 64!
--CRAM size in the CR/CSR space (bytes):
constant c_CRAM_SIZE : integer := 1024; -- remember to set properly the
-- "END_CRAM" register in the CR space
-- WB addr width:
constant c_addr_width : integer := 9;
constant DFS : integer := 2; -- for accessing at the ADEM's bit 2
constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0
-- Tclk in ns used to calculate the data transfer rate
constant c_clk_period : integer := 10;
-- add here the default boards ID:
constant c_SVEC_ID : integer := 408; -- 0x00000198
constant c_CERN_ID : integer := 524336; -- 0x080030
constant c_RevisionID : integer := 1; -- 0x00000001
--BoardID positions:
constant c_BOARD_ID_p1 : integer := 12;
constant c_BOARD_ID_p2 : integer := 13;
constant c_BOARD_ID_p3 : integer := 14;
constant c_BOARD_ID_p4 : integer := 15;
--ManufacturerID positions:
constant c_Manuf_ID_p1 : integer := 9;
constant c_Manuf_ID_p2 : integer := 10;
constant c_Manuf_ID_p3 : integer := 11;
--RevisionID positions:
constant c_Rev_ID_p1 : integer := 16;
constant c_Rev_ID_p2 : integer := 17;
constant c_Rev_ID_p3 : integer := 18;
constant c_Rev_ID_p4 : integer := 19;
--ProgramID positions:
constant c_Prog_ID_p : integer := 31;
constant c_svec_id : std_logic_vector(31 downto 0) := x"00000198";
constant c_cern_id : std_logic_vector(23 downto 0) := x"080030";
constant c_revision_id : std_logic_vector(31 downto 0) := x"00000001";
constant c_program_id : std_logic_vector( 7 downto 0) := x"5a";
constant DFS : integer := 2; -- for accessing at the ADEM's bit 2
constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0
-- AM table.
-- References:
......@@ -446,7 +424,7 @@ package vme64x_pack is
type t_FUNC_256b_array_std is
array (0 to 7) of std_logic_vector(255 downto 0); -- XAMCAP register array
type t_CSRarray is
type t_csr_array is
array(BAR downto WB32bits) of unsigned(7 downto 0);
type t_cr_array is
......@@ -460,30 +438,117 @@ package vme64x_pack is
A : natural
) return natural;
function f_set_CR_space (
BoardID : integer;
cr_default : t_cr_array;
ManufacturerID : integer;
RevisionID : integer;
ProgramID : integer
) return t_cr_array;
function f_latchDS (
clk_period : integer
) return integer;
function f_vme_cr_encode (
manufacturer_id : std_logic_vector( 23 downto 0);
board_id : std_logic_vector( 31 downto 0);
revision_id : std_logic_vector( 31 downto 0);
program_id : std_logic_vector( 7 downto 0);
ascii_ptr : std_logic_vector( 23 downto 0);
beg_user_cr : std_logic_vector( 23 downto 0);
end_user_cr : std_logic_vector( 23 downto 0);
beg_cram : std_logic_vector( 23 downto 0);
end_cram : std_logic_vector( 23 downto 0);
beg_user_csr : std_logic_vector( 23 downto 0);
end_user_csr : std_logic_vector( 23 downto 0);
beg_sn : std_logic_vector( 23 downto 0);
end_sn : std_logic_vector( 23 downto 0);
f0_adem : std_logic_vector( 31 downto 0);
f0_amcap : std_logic_vector( 63 downto 0);
f0_xamcap : std_logic_vector(255 downto 0);
f0_dawpr : std_logic_vector( 7 downto 0);
f1_adem : std_logic_vector( 31 downto 0);
f1_amcap : std_logic_vector( 63 downto 0);
f1_xamcap : std_logic_vector(255 downto 0);
f1_dawpr : std_logic_vector( 7 downto 0);
f2_adem : std_logic_vector( 31 downto 0);
f2_amcap : std_logic_vector( 63 downto 0);
f2_xamcap : std_logic_vector(255 downto 0);
f2_dawpr : std_logic_vector( 7 downto 0);
f3_adem : std_logic_vector( 31 downto 0);
f3_amcap : std_logic_vector( 63 downto 0);
f3_xamcap : std_logic_vector(255 downto 0);
f3_dawpr : std_logic_vector( 7 downto 0);
f4_adem : std_logic_vector( 31 downto 0);
f4_amcap : std_logic_vector( 63 downto 0);
f4_xamcap : std_logic_vector(255 downto 0);
f4_dawpr : std_logic_vector( 7 downto 0);
f5_adem : std_logic_vector( 31 downto 0);
f5_amcap : std_logic_vector( 63 downto 0);
f5_xamcap : std_logic_vector(255 downto 0);
f5_dawpr : std_logic_vector( 7 downto 0);
f6_adem : std_logic_vector( 31 downto 0);
f6_amcap : std_logic_vector( 63 downto 0);
f6_xamcap : std_logic_vector(255 downto 0);
f6_dawpr : std_logic_vector( 7 downto 0);
f7_adem : std_logic_vector( 31 downto 0);
f7_amcap : std_logic_vector( 63 downto 0);
f7_xamcap : std_logic_vector(255 downto 0);
f7_dawpr : std_logic_vector( 7 downto 0)
) return t_cr_array;
function f_size (
A : std_logic_vector;
B : std_logic_vector
) return integer;
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
component VME64xCore_Top
generic (
g_wb_data_width : integer := 32;
g_wb_addr_width : integer := 64;
g_CRAM_SIZE : integer := 1024;
g_adem_a24 : std_logic_vector(31 downto 0);
g_adem_a32 : std_logic_vector(31 downto 0);
g_clock : integer
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
);
port (
clk_i : in std_logic;
......@@ -531,10 +596,10 @@ package vme64x_pack is
component VME_bus is
generic (
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_cram_size : integer
);
port (
clk_i : in std_logic;
......@@ -684,13 +749,9 @@ package vme64x_pack is
component VME_CR_CSR_Space is
generic (
g_cram_size : integer := c_CRAM_SIZE;
g_wb_data_width : integer := c_width;
g_CRspace : t_cr_array;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID;
g_RevisionID : integer := c_RevisionID;
g_ProgramID : integer := 96
g_cram_size : integer;
g_wb_data_width : integer;
g_cr_space : t_cr_array
);
port (
clk_i : in std_logic;
......@@ -766,8 +827,8 @@ package vme64x_pack is
component VME_Wb_master is
generic (
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
g_wb_data_width : integer;
g_wb_addr_width : integer
);
port (
memReq_i : in std_logic;
......@@ -871,8 +932,8 @@ package vme64x_pack is
component VME_CRAM is
generic (
dl : integer := 8;
al : integer := f_log2_size(c_CRAM_SIZE)
dl : integer;
al : integer
);
port (
clk : in std_logic;
......@@ -897,43 +958,6 @@ package body vme64x_pack is
return(63);
end function f_log2_size;
function f_set_CR_space (
BoardID : integer;
cr_default : t_cr_array;
ManufacturerID : integer;
RevisionID : integer;
ProgramID : integer
) return t_cr_array is
variable v_CR_space : t_cr_array(2**12 downto 0);
variable v_BoardID : std_logic_vector(31 downto 0);
variable v_ManufacturerID : std_logic_vector(23 downto 0);
variable v_RevisionID : std_logic_vector(31 downto 0);
variable v_ProgramID : std_logic_vector(7 downto 0);
begin
v_BoardID := std_logic_vector(to_unsigned(BoardID, 32));
v_ManufacturerID := std_logic_vector(to_unsigned(ManufacturerID, 24));
v_RevisionID := std_logic_vector(to_unsigned(RevisionID, 32));
v_ProgramID := std_logic_vector(to_unsigned(ProgramID, 8));
for i in cr_default'range loop
case i is
when c_BOARD_ID_p1 => v_CR_space(i) := v_BoardID(31 downto 24);
when c_BOARD_ID_p2 => v_CR_space(i) := v_BoardID(23 downto 16);
when c_BOARD_ID_p3 => v_CR_space(i) := v_BoardID(15 downto 8);
when c_BOARD_ID_p4 => v_CR_space(i) := v_BoardID(7 downto 0);
when c_Manuf_ID_p1 => v_CR_space(i) := v_ManufacturerID(23 downto 16);
when c_Manuf_ID_p2 => v_CR_space(i) := v_ManufacturerID(15 downto 8);
when c_Manuf_ID_p3 => v_CR_space(i) := v_ManufacturerID(7 downto 0);
when c_Rev_ID_p1 => v_CR_space(i) := v_RevisionID(31 downto 24);
when c_Rev_ID_p2 => v_CR_space(i) := v_RevisionID(23 downto 16);
when c_Rev_ID_p3 => v_CR_space(i) := v_RevisionID(15 downto 8);
when c_Rev_ID_p4 => v_CR_space(i) := v_RevisionID(7 downto 0);
when c_Prog_ID_p => v_CR_space(i) := v_ProgramID(7 downto 0);
when others => v_CR_space(i) := cr_default(i);
end case;
end loop;
return(v_CR_space);
end function f_set_CR_space;
function f_latchDS (clk_period : integer) return integer is
begin
for I in 1 to 4 loop
......@@ -944,4 +968,522 @@ package body vme64x_pack is
return(4); -- works for up to 200 MHz
end function f_latchDS;
function f_vme_cr_encode (
manufacturer_id : std_logic_vector( 23 downto 0);
board_id : std_logic_vector( 31 downto 0);
revision_id : std_logic_vector( 31 downto 0);
program_id : std_logic_vector( 7 downto 0);
ascii_ptr : std_logic_vector( 23 downto 0);
beg_user_cr : std_logic_vector( 23 downto 0);
end_user_cr : std_logic_vector( 23 downto 0);
beg_cram : std_logic_vector( 23 downto 0);
end_cram : std_logic_vector( 23 downto 0);
beg_user_csr : std_logic_vector( 23 downto 0);
end_user_csr : std_logic_vector( 23 downto 0);
beg_sn : std_logic_vector( 23 downto 0);
end_sn : std_logic_vector( 23 downto 0);
f0_adem : std_logic_vector( 31 downto 0);
f0_amcap : std_logic_vector( 63 downto 0);
f0_xamcap : std_logic_vector(255 downto 0);
f0_dawpr : std_logic_vector( 7 downto 0);
f1_adem : std_logic_vector( 31 downto 0);
f1_amcap : std_logic_vector( 63 downto 0);
f1_xamcap : std_logic_vector(255 downto 0);
f1_dawpr : std_logic_vector( 7 downto 0);
f2_adem : std_logic_vector( 31 downto 0);
f2_amcap : std_logic_vector( 63 downto 0);
f2_xamcap : std_logic_vector(255 downto 0);
f2_dawpr : std_logic_vector( 7 downto 0);
f3_adem : std_logic_vector( 31 downto 0);
f3_amcap : std_logic_vector( 63 downto 0);
f3_xamcap : std_logic_vector(255 downto 0);
f3_dawpr : std_logic_vector( 7 downto 0);
f4_adem : std_logic_vector( 31 downto 0);
f4_amcap : std_logic_vector( 63 downto 0);
f4_xamcap : std_logic_vector(255 downto 0);
f4_dawpr : std_logic_vector( 7 downto 0);
f5_adem : std_logic_vector( 31 downto 0);
f5_amcap : std_logic_vector( 63 downto 0);
f5_xamcap : std_logic_vector(255 downto 0);
f5_dawpr : std_logic_vector( 7 downto 0);
f6_adem : std_logic_vector( 31 downto 0);
f6_amcap : std_logic_vector( 63 downto 0);
f6_xamcap : std_logic_vector(255 downto 0);
f6_dawpr : std_logic_vector( 7 downto 0);
f7_adem : std_logic_vector( 31 downto 0);
f7_amcap : std_logic_vector( 63 downto 0);
f7_xamcap : std_logic_vector(255 downto 0);
f7_dawpr : std_logic_vector( 7 downto 0)
) return t_cr_array
is
variable cr : t_cr_array(1023 downto 0) := (others => x"00");
variable crc : unsigned(7 downto 0) := x"00";
begin
cr(16#001#) := x"00"; -- Length of CR (excluding CRC)
cr(16#002#) := x"03";
cr(16#003#) := x"ff";
cr(16#004#) := x"81"; -- CR data access width
cr(16#005#) := x"81"; -- CSR data access width
cr(16#006#) := x"02"; -- CR/CSR Space Specification ID
cr(16#007#) := x"43"; -- ASCII "C"
cr(16#008#) := x"52"; -- ASCII "R"
cr(16#009#) := manufacturer_id(23 downto 16);
cr(16#00A#) := manufacturer_id(15 downto 8);
cr(16#00B#) := manufacturer_id( 7 downto 0);
cr(16#00C#) := board_id(31 downto 24);
cr(16#00D#) := board_id(23 downto 16);
cr(16#00E#) := board_id(15 downto 8);
cr(16#00F#) := board_id( 7 downto 0);
cr(16#010#) := revision_id(31 downto 24);
cr(16#011#) := revision_id(23 downto 16);
cr(16#012#) := revision_id(15 downto 8);
cr(16#013#) := revision_id( 7 downto 0);
cr(16#014#) := ascii_ptr(23 downto 16);
cr(16#015#) := ascii_ptr(15 downto 8);
cr(16#016#) := ascii_ptr( 7 downto 0);
cr(16#01F#) := program_id;
cr(16#020#) := beg_user_cr(23 downto 16);
cr(16#021#) := beg_user_cr(15 downto 8);
cr(16#022#) := beg_user_cr( 7 downto 0);
cr(16#023#) := end_user_cr(23 downto 16);
cr(16#024#) := end_user_cr(15 downto 8);
cr(16#025#) := end_user_cr( 7 downto 0);
cr(16#026#) := beg_cram(23 downto 16);
cr(16#027#) := beg_cram(15 downto 8);
cr(16#028#) := beg_cram( 7 downto 0);
cr(16#029#) := end_cram(23 downto 16);
cr(16#02A#) := end_cram(15 downto 8);
cr(16#02B#) := end_cram( 7 downto 0);
cr(16#02C#) := beg_user_csr(23 downto 16);
cr(16#02D#) := beg_user_csr(15 downto 8);
cr(16#02E#) := beg_user_csr( 7 downto 0);
cr(16#02F#) := end_user_csr(23 downto 16);
cr(16#030#) := end_user_csr(15 downto 8);
cr(16#031#) := end_user_csr( 7 downto 0);
cr(16#032#) := beg_sn(23 downto 16);
cr(16#033#) := beg_sn(15 downto 8);
cr(16#034#) := beg_sn( 7 downto 0);
cr(16#035#) := end_sn(23 downto 16);
cr(16#036#) := end_sn(15 downto 8);
cr(16#037#) := end_sn( 7 downto 0);
cr(16#03F#) := x"81"; -- CRAM data access width
cr(16#040#) := f0_dawpr;
cr(16#041#) := f1_dawpr;
cr(16#042#) := f2_dawpr;
cr(16#043#) := f3_dawpr;
cr(16#044#) := f4_dawpr;
cr(16#045#) := f5_dawpr;
cr(16#046#) := f6_dawpr;
cr(16#047#) := f7_dawpr;
cr(16#048#) := f0_amcap(63 downto 56);
cr(16#049#) := f0_amcap(55 downto 48);
cr(16#04A#) := f0_amcap(47 downto 40);
cr(16#04B#) := f0_amcap(39 downto 32);
cr(16#04C#) := f0_amcap(31 downto 24);
cr(16#04D#) := f0_amcap(23 downto 16);
cr(16#04E#) := f0_amcap(15 downto 8);
cr(16#04F#) := f0_amcap( 7 downto 0);
cr(16#050#) := f1_amcap(63 downto 56);
cr(16#051#) := f1_amcap(55 downto 48);
cr(16#052#) := f1_amcap(47 downto 40);
cr(16#053#) := f1_amcap(39 downto 32);
cr(16#054#) := f1_amcap(31 downto 24);
cr(16#055#) := f1_amcap(23 downto 16);
cr(16#056#) := f1_amcap(15 downto 8);
cr(16#057#) := f1_amcap( 7 downto 0);
cr(16#058#) := f2_amcap(63 downto 56);
cr(16#059#) := f2_amcap(55 downto 48);
cr(16#05A#) := f2_amcap(47 downto 40);
cr(16#05B#) := f2_amcap(39 downto 32);
cr(16#05C#) := f2_amcap(31 downto 24);
cr(16#05D#) := f2_amcap(23 downto 16);
cr(16#05E#) := f2_amcap(15 downto 8);
cr(16#05F#) := f2_amcap( 7 downto 0);
cr(16#060#) := f3_amcap(63 downto 56);
cr(16#061#) := f3_amcap(55 downto 48);
cr(16#062#) := f3_amcap(47 downto 40);
cr(16#063#) := f3_amcap(39 downto 32);
cr(16#064#) := f3_amcap(31 downto 24);
cr(16#065#) := f3_amcap(23 downto 16);
cr(16#066#) := f3_amcap(15 downto 8);
cr(16#067#) := f3_amcap( 7 downto 0);
cr(16#068#) := f4_amcap(63 downto 56);
cr(16#069#) := f4_amcap(55 downto 48);
cr(16#06A#) := f4_amcap(47 downto 40);
cr(16#06B#) := f4_amcap(39 downto 32);
cr(16#06C#) := f4_amcap(31 downto 24);
cr(16#06D#) := f4_amcap(23 downto 16);
cr(16#06E#) := f4_amcap(15 downto 8);
cr(16#06F#) := f4_amcap( 7 downto 0);
cr(16#070#) := f5_amcap(63 downto 56);
cr(16#071#) := f5_amcap(55 downto 48);
cr(16#072#) := f5_amcap(47 downto 40);
cr(16#073#) := f5_amcap(39 downto 32);
cr(16#074#) := f5_amcap(31 downto 24);
cr(16#075#) := f5_amcap(23 downto 16);
cr(16#076#) := f5_amcap(15 downto 8);
cr(16#077#) := f5_amcap( 7 downto 0);
cr(16#078#) := f6_amcap(63 downto 56);
cr(16#079#) := f6_amcap(55 downto 48);
cr(16#07A#) := f6_amcap(47 downto 40);
cr(16#07B#) := f6_amcap(39 downto 32);
cr(16#07C#) := f6_amcap(31 downto 24);
cr(16#07D#) := f6_amcap(23 downto 16);
cr(16#07E#) := f6_amcap(15 downto 8);
cr(16#07F#) := f6_amcap( 7 downto 0);
cr(16#080#) := f7_amcap(63 downto 56);
cr(16#081#) := f7_amcap(55 downto 48);
cr(16#082#) := f7_amcap(47 downto 40);
cr(16#083#) := f7_amcap(39 downto 32);
cr(16#084#) := f7_amcap(31 downto 24);
cr(16#085#) := f7_amcap(23 downto 16);
cr(16#086#) := f7_amcap(15 downto 8);
cr(16#087#) := f7_amcap( 7 downto 0);
cr(16#088#) := f0_xamcap(255 downto 248);
cr(16#089#) := f0_xamcap(247 downto 240);
cr(16#08A#) := f0_xamcap(239 downto 232);
cr(16#08B#) := f0_xamcap(231 downto 224);
cr(16#08C#) := f0_xamcap(223 downto 216);
cr(16#08D#) := f0_xamcap(215 downto 208);
cr(16#08E#) := f0_xamcap(207 downto 200);
cr(16#08F#) := f0_xamcap(199 downto 192);
cr(16#090#) := f0_xamcap(191 downto 184);
cr(16#091#) := f0_xamcap(183 downto 176);
cr(16#092#) := f0_xamcap(175 downto 168);
cr(16#093#) := f0_xamcap(167 downto 160);
cr(16#094#) := f0_xamcap(159 downto 152);
cr(16#095#) := f0_xamcap(151 downto 144);
cr(16#096#) := f0_xamcap(143 downto 136);
cr(16#097#) := f0_xamcap(135 downto 128);
cr(16#098#) := f0_xamcap(127 downto 120);
cr(16#099#) := f0_xamcap(119 downto 112);
cr(16#09A#) := f0_xamcap(111 downto 104);
cr(16#09B#) := f0_xamcap(103 downto 96);
cr(16#09C#) := f0_xamcap( 95 downto 88);
cr(16#09D#) := f0_xamcap( 87 downto 80);
cr(16#09E#) := f0_xamcap( 79 downto 72);
cr(16#09F#) := f0_xamcap( 71 downto 64);
cr(16#0A0#) := f0_xamcap( 63 downto 56);
cr(16#0A1#) := f0_xamcap( 55 downto 48);
cr(16#0A2#) := f0_xamcap( 47 downto 40);
cr(16#0A3#) := f0_xamcap( 39 downto 32);
cr(16#0A4#) := f0_xamcap( 31 downto 24);
cr(16#0A5#) := f0_xamcap( 23 downto 16);
cr(16#0A6#) := f0_xamcap( 15 downto 8);
cr(16#0A7#) := f0_xamcap( 7 downto 0);
cr(16#0A8#) := f1_xamcap(255 downto 248);
cr(16#0A9#) := f1_xamcap(247 downto 240);
cr(16#0AA#) := f1_xamcap(239 downto 232);
cr(16#0AB#) := f1_xamcap(231 downto 224);
cr(16#0AC#) := f1_xamcap(223 downto 216);
cr(16#0AD#) := f1_xamcap(215 downto 208);
cr(16#0AE#) := f1_xamcap(207 downto 200);
cr(16#0AF#) := f1_xamcap(199 downto 192);
cr(16#0B0#) := f1_xamcap(191 downto 184);
cr(16#0B1#) := f1_xamcap(183 downto 176);
cr(16#0B2#) := f1_xamcap(175 downto 168);
cr(16#0B3#) := f1_xamcap(167 downto 160);
cr(16#0B4#) := f1_xamcap(159 downto 152);
cr(16#0B5#) := f1_xamcap(151 downto 144);
cr(16#0B6#) := f1_xamcap(143 downto 136);
cr(16#0B7#) := f1_xamcap(135 downto 128);
cr(16#0B8#) := f1_xamcap(127 downto 120);
cr(16#0B9#) := f1_xamcap(119 downto 112);
cr(16#0BA#) := f1_xamcap(111 downto 104);
cr(16#0BB#) := f1_xamcap(103 downto 96);
cr(16#0BC#) := f1_xamcap( 95 downto 88);
cr(16#0BD#) := f1_xamcap( 87 downto 80);
cr(16#0BE#) := f1_xamcap( 79 downto 72);
cr(16#0BF#) := f1_xamcap( 71 downto 64);
cr(16#0C0#) := f1_xamcap( 63 downto 56);
cr(16#0C1#) := f1_xamcap( 55 downto 48);
cr(16#0C2#) := f1_xamcap( 47 downto 40);
cr(16#0C3#) := f1_xamcap( 39 downto 32);
cr(16#0C4#) := f1_xamcap( 31 downto 24);
cr(16#0C5#) := f1_xamcap( 23 downto 16);
cr(16#0C6#) := f1_xamcap( 15 downto 8);
cr(16#0C7#) := f1_xamcap( 7 downto 0);
cr(16#0C8#) := f2_xamcap(255 downto 248);
cr(16#0C9#) := f2_xamcap(247 downto 240);
cr(16#0CA#) := f2_xamcap(239 downto 232);
cr(16#0CB#) := f2_xamcap(231 downto 224);
cr(16#0CC#) := f2_xamcap(223 downto 216);
cr(16#0CD#) := f2_xamcap(215 downto 208);
cr(16#0CE#) := f2_xamcap(207 downto 200);
cr(16#0CF#) := f2_xamcap(199 downto 192);
cr(16#0D0#) := f2_xamcap(191 downto 184);
cr(16#0D1#) := f2_xamcap(183 downto 176);
cr(16#0D2#) := f2_xamcap(175 downto 168);
cr(16#0D3#) := f2_xamcap(167 downto 160);
cr(16#0D4#) := f2_xamcap(159 downto 152);
cr(16#0D5#) := f2_xamcap(151 downto 144);
cr(16#0D6#) := f2_xamcap(143 downto 136);
cr(16#0D7#) := f2_xamcap(135 downto 128);
cr(16#0D8#) := f2_xamcap(127 downto 120);
cr(16#0D9#) := f2_xamcap(119 downto 112);
cr(16#0DA#) := f2_xamcap(111 downto 104);
cr(16#0DB#) := f2_xamcap(103 downto 96);
cr(16#0DC#) := f2_xamcap( 95 downto 88);
cr(16#0DD#) := f2_xamcap( 87 downto 80);
cr(16#0DE#) := f2_xamcap( 79 downto 72);
cr(16#0DF#) := f2_xamcap( 71 downto 64);
cr(16#0E0#) := f2_xamcap( 63 downto 56);
cr(16#0E1#) := f2_xamcap( 55 downto 48);
cr(16#0E2#) := f2_xamcap( 47 downto 40);
cr(16#0E3#) := f2_xamcap( 39 downto 32);
cr(16#0E4#) := f2_xamcap( 31 downto 24);
cr(16#0E5#) := f2_xamcap( 23 downto 16);
cr(16#0E6#) := f2_xamcap( 15 downto 8);
cr(16#0E7#) := f2_xamcap( 7 downto 0);
cr(16#0E8#) := f3_xamcap(255 downto 248);
cr(16#0E9#) := f3_xamcap(247 downto 240);
cr(16#0EA#) := f3_xamcap(239 downto 232);
cr(16#0EB#) := f3_xamcap(231 downto 224);
cr(16#0EC#) := f3_xamcap(223 downto 216);
cr(16#0ED#) := f3_xamcap(215 downto 208);
cr(16#0EE#) := f3_xamcap(207 downto 200);
cr(16#0EF#) := f3_xamcap(199 downto 192);
cr(16#0F0#) := f3_xamcap(191 downto 184);
cr(16#0F1#) := f3_xamcap(183 downto 176);
cr(16#0F2#) := f3_xamcap(175 downto 168);
cr(16#0F3#) := f3_xamcap(167 downto 160);
cr(16#0F4#) := f3_xamcap(159 downto 152);
cr(16#0F5#) := f3_xamcap(151 downto 144);
cr(16#0F6#) := f3_xamcap(143 downto 136);
cr(16#0F7#) := f3_xamcap(135 downto 128);
cr(16#0F8#) := f3_xamcap(127 downto 120);
cr(16#0F9#) := f3_xamcap(119 downto 112);
cr(16#0FA#) := f3_xamcap(111 downto 104);
cr(16#0FB#) := f3_xamcap(103 downto 96);
cr(16#0FC#) := f3_xamcap( 95 downto 88);
cr(16#0FD#) := f3_xamcap( 87 downto 80);
cr(16#0FE#) := f3_xamcap( 79 downto 72);
cr(16#0FF#) := f3_xamcap( 71 downto 64);
cr(16#100#) := f3_xamcap( 63 downto 56);
cr(16#101#) := f3_xamcap( 55 downto 48);
cr(16#102#) := f3_xamcap( 47 downto 40);
cr(16#103#) := f3_xamcap( 39 downto 32);
cr(16#104#) := f3_xamcap( 31 downto 24);
cr(16#105#) := f3_xamcap( 23 downto 16);
cr(16#106#) := f3_xamcap( 15 downto 8);
cr(16#107#) := f3_xamcap( 7 downto 0);
cr(16#108#) := f4_xamcap(255 downto 248);
cr(16#109#) := f4_xamcap(247 downto 240);
cr(16#10A#) := f4_xamcap(239 downto 232);
cr(16#10B#) := f4_xamcap(231 downto 224);
cr(16#10C#) := f4_xamcap(223 downto 216);
cr(16#10D#) := f4_xamcap(215 downto 208);
cr(16#10E#) := f4_xamcap(207 downto 200);
cr(16#10F#) := f4_xamcap(199 downto 192);
cr(16#110#) := f4_xamcap(191 downto 184);
cr(16#111#) := f4_xamcap(183 downto 176);
cr(16#112#) := f4_xamcap(175 downto 168);
cr(16#113#) := f4_xamcap(167 downto 160);
cr(16#114#) := f4_xamcap(159 downto 152);
cr(16#115#) := f4_xamcap(151 downto 144);
cr(16#116#) := f4_xamcap(143 downto 136);
cr(16#117#) := f4_xamcap(135 downto 128);
cr(16#118#) := f4_xamcap(127 downto 120);
cr(16#119#) := f4_xamcap(119 downto 112);
cr(16#11A#) := f4_xamcap(111 downto 104);
cr(16#11B#) := f4_xamcap(103 downto 96);
cr(16#11C#) := f4_xamcap( 95 downto 88);
cr(16#11D#) := f4_xamcap( 87 downto 80);
cr(16#11E#) := f4_xamcap( 79 downto 72);
cr(16#11F#) := f4_xamcap( 71 downto 64);
cr(16#120#) := f4_xamcap( 63 downto 56);
cr(16#121#) := f4_xamcap( 55 downto 48);
cr(16#122#) := f4_xamcap( 47 downto 40);
cr(16#123#) := f4_xamcap( 39 downto 32);
cr(16#124#) := f4_xamcap( 31 downto 24);
cr(16#125#) := f4_xamcap( 23 downto 16);
cr(16#126#) := f4_xamcap( 15 downto 8);
cr(16#127#) := f4_xamcap( 7 downto 0);
cr(16#128#) := f5_xamcap(255 downto 248);
cr(16#129#) := f5_xamcap(247 downto 240);
cr(16#12A#) := f5_xamcap(239 downto 232);
cr(16#12B#) := f5_xamcap(231 downto 224);
cr(16#12C#) := f5_xamcap(223 downto 216);
cr(16#12D#) := f5_xamcap(215 downto 208);
cr(16#12E#) := f5_xamcap(207 downto 200);
cr(16#12F#) := f5_xamcap(199 downto 192);
cr(16#130#) := f5_xamcap(191 downto 184);
cr(16#131#) := f5_xamcap(183 downto 176);
cr(16#132#) := f5_xamcap(175 downto 168);
cr(16#133#) := f5_xamcap(167 downto 160);
cr(16#134#) := f5_xamcap(159 downto 152);
cr(16#135#) := f5_xamcap(151 downto 144);
cr(16#136#) := f5_xamcap(143 downto 136);
cr(16#137#) := f5_xamcap(135 downto 128);
cr(16#138#) := f5_xamcap(127 downto 120);
cr(16#139#) := f5_xamcap(119 downto 112);
cr(16#13A#) := f5_xamcap(111 downto 104);
cr(16#13B#) := f5_xamcap(103 downto 96);
cr(16#13C#) := f5_xamcap( 95 downto 88);
cr(16#13D#) := f5_xamcap( 87 downto 80);
cr(16#13E#) := f5_xamcap( 79 downto 72);
cr(16#13F#) := f5_xamcap( 71 downto 64);
cr(16#140#) := f5_xamcap( 63 downto 56);
cr(16#141#) := f5_xamcap( 55 downto 48);
cr(16#142#) := f5_xamcap( 47 downto 40);
cr(16#143#) := f5_xamcap( 39 downto 32);
cr(16#144#) := f5_xamcap( 31 downto 24);
cr(16#145#) := f5_xamcap( 23 downto 16);
cr(16#146#) := f5_xamcap( 15 downto 8);
cr(16#147#) := f5_xamcap( 7 downto 0);
cr(16#148#) := f6_xamcap(255 downto 248);
cr(16#149#) := f6_xamcap(247 downto 240);
cr(16#14A#) := f6_xamcap(239 downto 232);
cr(16#14B#) := f6_xamcap(231 downto 224);
cr(16#14C#) := f6_xamcap(223 downto 216);
cr(16#14D#) := f6_xamcap(215 downto 208);
cr(16#14E#) := f6_xamcap(207 downto 200);
cr(16#14F#) := f6_xamcap(199 downto 192);
cr(16#150#) := f6_xamcap(191 downto 184);
cr(16#151#) := f6_xamcap(183 downto 176);
cr(16#152#) := f6_xamcap(175 downto 168);
cr(16#153#) := f6_xamcap(167 downto 160);
cr(16#154#) := f6_xamcap(159 downto 152);
cr(16#155#) := f6_xamcap(151 downto 144);
cr(16#156#) := f6_xamcap(143 downto 136);
cr(16#157#) := f6_xamcap(135 downto 128);
cr(16#158#) := f6_xamcap(127 downto 120);
cr(16#159#) := f6_xamcap(119 downto 112);
cr(16#15A#) := f6_xamcap(111 downto 104);
cr(16#15B#) := f6_xamcap(103 downto 96);
cr(16#15C#) := f6_xamcap( 95 downto 88);
cr(16#15D#) := f6_xamcap( 87 downto 80);
cr(16#15E#) := f6_xamcap( 79 downto 72);
cr(16#15F#) := f6_xamcap( 71 downto 64);
cr(16#160#) := f6_xamcap( 63 downto 56);
cr(16#161#) := f6_xamcap( 55 downto 48);
cr(16#162#) := f6_xamcap( 47 downto 40);
cr(16#163#) := f6_xamcap( 39 downto 32);
cr(16#164#) := f6_xamcap( 31 downto 24);
cr(16#165#) := f6_xamcap( 23 downto 16);
cr(16#166#) := f6_xamcap( 15 downto 8);
cr(16#167#) := f6_xamcap( 7 downto 0);
cr(16#168#) := f7_xamcap(255 downto 248);
cr(16#169#) := f7_xamcap(247 downto 240);
cr(16#16A#) := f7_xamcap(239 downto 232);
cr(16#16B#) := f7_xamcap(231 downto 224);
cr(16#16C#) := f7_xamcap(223 downto 216);
cr(16#16D#) := f7_xamcap(215 downto 208);
cr(16#16E#) := f7_xamcap(207 downto 200);
cr(16#16F#) := f7_xamcap(199 downto 192);
cr(16#170#) := f7_xamcap(191 downto 184);
cr(16#171#) := f7_xamcap(183 downto 176);
cr(16#172#) := f7_xamcap(175 downto 168);
cr(16#173#) := f7_xamcap(167 downto 160);
cr(16#174#) := f7_xamcap(159 downto 152);
cr(16#175#) := f7_xamcap(151 downto 144);
cr(16#176#) := f7_xamcap(143 downto 136);
cr(16#177#) := f7_xamcap(135 downto 128);
cr(16#178#) := f7_xamcap(127 downto 120);
cr(16#179#) := f7_xamcap(119 downto 112);
cr(16#17A#) := f7_xamcap(111 downto 104);
cr(16#17B#) := f7_xamcap(103 downto 96);
cr(16#17C#) := f7_xamcap( 95 downto 88);
cr(16#17D#) := f7_xamcap( 87 downto 80);
cr(16#17E#) := f7_xamcap( 79 downto 72);
cr(16#17F#) := f7_xamcap( 71 downto 64);
cr(16#180#) := f7_xamcap( 63 downto 56);
cr(16#181#) := f7_xamcap( 55 downto 48);
cr(16#182#) := f7_xamcap( 47 downto 40);
cr(16#183#) := f7_xamcap( 39 downto 32);
cr(16#184#) := f7_xamcap( 31 downto 24);
cr(16#185#) := f7_xamcap( 23 downto 16);
cr(16#186#) := f7_xamcap( 15 downto 8);
cr(16#187#) := f7_xamcap( 7 downto 0);
cr(16#188#) := f0_adem(31 downto 24);
cr(16#189#) := f0_adem(23 downto 16);
cr(16#18A#) := f0_adem(15 downto 8);
cr(16#18B#) := f0_adem( 7 downto 0);
cr(16#18C#) := f1_adem(31 downto 24);
cr(16#18D#) := f1_adem(23 downto 16);
cr(16#18E#) := f1_adem(15 downto 8);
cr(16#18F#) := f1_adem( 7 downto 0);
cr(16#190#) := f2_adem(31 downto 24);
cr(16#191#) := f2_adem(23 downto 16);
cr(16#192#) := f2_adem(15 downto 8);
cr(16#193#) := f2_adem( 7 downto 0);
cr(16#194#) := f3_adem(31 downto 24);
cr(16#195#) := f3_adem(23 downto 16);
cr(16#196#) := f3_adem(15 downto 8);
cr(16#197#) := f3_adem( 7 downto 0);
cr(16#198#) := f4_adem(31 downto 24);
cr(16#199#) := f4_adem(23 downto 16);
cr(16#19A#) := f4_adem(15 downto 8);
cr(16#19B#) := f4_adem( 7 downto 0);
cr(16#19C#) := f5_adem(31 downto 24);
cr(16#19D#) := f5_adem(23 downto 16);
cr(16#19E#) := f5_adem(15 downto 8);
cr(16#19F#) := f5_adem( 7 downto 0);
cr(16#1A0#) := f6_adem(31 downto 24);
cr(16#1A1#) := f6_adem(23 downto 16);
cr(16#1A2#) := f6_adem(15 downto 8);
cr(16#1A3#) := f6_adem( 7 downto 0);
cr(16#1A4#) := f7_adem(31 downto 24);
cr(16#1A5#) := f7_adem(23 downto 16);
cr(16#1A6#) := f7_adem(15 downto 8);
cr(16#1A7#) := f7_adem( 7 downto 0);
-- Calculate CRC
for i in 1 to cr'length-1 loop
crc := crc + unsigned(cr(i));
end loop;
cr(16#000#) := std_logic_vector(crc);
return cr;
end;
function f_size (
A : std_logic_vector;
B : std_logic_vector
) return integer is
begin
return ((to_integer(unsigned(B)) - to_integer(unsigned(A))) / 4) + 1;
end;
end vme64x_pack;
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @ 6d88bf97
......@@ -37,9 +37,69 @@ use work.vme64x_pack.all;
entity xvme64x_core is
generic (
g_clock_freq : integer := 62500000;
g_adem_a24 : std_logic_vector(31 downto 0) := x"fff80000";
g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
g_clock_period : integer := c_clk_period;
g_wb_data_width : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_addr_width;
-- CR/CSR
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001000";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -89,9 +149,54 @@ begin -- wrapper
U_Wrapped_VME : VME64xCore_Top
generic map (
g_adem_a32 => g_adem_a32,
g_adem_a24 => g_adem_a24,
g_clock => g_clock_freq
g_clock => g_clock_period,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_manufacturer_id => g_manufacturer_id,
g_board_id => g_board_id,
g_revision_id => g_revision_id,
g_program_id => g_program_id,
g_ascii_ptr => g_ascii_ptr,
g_beg_user_cr => g_beg_user_cr,
g_end_user_cr => g_end_user_cr,
g_beg_cram => g_beg_cram,
g_end_cram => g_end_cram,
g_beg_user_csr => g_beg_user_csr,
g_end_user_csr => g_end_user_csr,
g_beg_sn => g_beg_sn,
g_end_sn => g_end_sn,
g_f0_adem => g_f0_adem,
g_f0_amcap => g_f0_amcap,
g_f0_xamcap => g_f0_xamcap,
g_f0_dawpr => g_f0_dawpr,
g_f1_adem => g_f1_adem,
g_f1_amcap => g_f1_amcap,
g_f1_xamcap => g_f1_xamcap,
g_f1_dawpr => g_f1_dawpr,
g_f2_adem => g_f2_adem,
g_f2_amcap => g_f2_amcap,
g_f2_xamcap => g_f2_xamcap,
g_f2_dawpr => g_f2_dawpr,
g_f3_adem => g_f3_adem,
g_f3_amcap => g_f3_amcap,
g_f3_xamcap => g_f3_xamcap,
g_f3_dawpr => g_f3_dawpr,
g_f4_adem => g_f4_adem,
g_f4_amcap => g_f4_amcap,
g_f4_xamcap => g_f4_xamcap,
g_f4_dawpr => g_f4_dawpr,
g_f5_adem => g_f5_adem,
g_f5_amcap => g_f5_amcap,
g_f5_xamcap => g_f5_xamcap,
g_f5_dawpr => g_f5_dawpr,
g_f6_adem => g_f6_adem,
g_f6_amcap => g_f6_amcap,
g_f6_xamcap => g_f6_xamcap,
g_f6_dawpr => g_f6_dawpr,
g_f7_adem => g_f7_adem,
g_f7_amcap => g_f7_amcap,
g_f7_xamcap => g_f7_xamcap,
g_f7_dawpr => g_f7_dawpr
)
port map (
clk_i => clk_i,
......
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @ 6d88bf97
......@@ -78,9 +78,54 @@ package xvme64x_core_pkg is
------------------------------------------------------------------------------
component xvme64x_core
generic (
g_clock_freq : integer := 62500000;
g_adem_a24 : std_logic_vector(31 downto 0) := x"fff80000";
g_adem_a32 : std_logic_vector(31 downto 0) := x"ff000000"
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
);
port (
clk_i : in std_logic;
......@@ -120,27 +165,6 @@ package xvme64x_core_pkg is
);
end component xvme64x_core;
component xvme64x_core_structs is
generic (
g_wb_data_width : integer := 32;
g_wb_addr_width : integer := 64;
g_cram_size : integer := 1024;
g_window_size_a24 : std_logic_vector(31 downto 0) := x"00080000";
g_window_size_a32 : std_logic_vector(31 downto 0) := x"00080000"
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
vme_i : in t_vme64x_in;
vme_o : out t_vme64x_out;
vme_b : inout t_vme64x_bidir;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic
);
end component xvme64x_core_structs;
end xvme64x_core_pkg;
package body xvme64x_core_pkg is
......
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