VME_IRQ_Controller: correctly handle interrupts triggered simultaneously by multiple cards.

Also made the IRQ line level sensitive and applied retry timer. This is a rewrite of the IRQ controller, the whole core needs to be checked again and possibly rewritten too.

VME_IRQ_Controller: correctly handle interrupts triggered simultaneously by multiple cards.
Also made the IRQ line level sensitive and applied retry timer. This is a rewrite of the IRQ controller, the whole core needs to be checked again and possibly rewritten too.
8006dbda · Tomasz Wlostowski · 35164028 · 8006dbda · 8006dbda · 8006dbda
Commit 8006dbda authored Nov 28, 2013 by Tomasz Wlostowski
Showing with 161 additions and 339 deletions

VME64xCore_Top.vhd hdl/vme64x-core/rtl/VME64xCore_Top.vhd +3 -2

VME_IRQ_Controller.vhd hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd +144 -323

vme64x_pack.vhd hdl/vme64x-core/rtl/vme64x_pack.vhd +14 -14

No files found.
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
@@ -414,14 +414,15 @@ begin
 --------------------------------------------------------------------------------
  --  Interrupter
  Inst_VME_IRQ_Controller : VME_IRQ_Controller
+    generic map (
+      g_retry_timeout => 62500 -- 1ms timeout
+      )
    port map(
      clk_i           => clk_i,
      reset_n_i       => s_reset_IRQ,   -- asserted when low
      VME_IACKIN_n_i  => VME_IACKIN_n_oversampled,
      VME_AS_n_i      => VME_AS_n_oversampled,
-      VME_AS1_n_i     => VME_AS_n_i,
      VME_DS_n_i      => VME_DS_n_oversampled,
-      VME_LWORD_n_i   => VME_LWORD_n_i,
      VME_ADDR_123_i  => VME_ADDR_i(3 downto 1),
      INT_Level_i     => s_INT_Level,
      INT_Vector_i    => s_INT_Vector ,

--- a/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
+++ b/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
--- a/hdl/vme64x-core/rtl/vme64x_pack.vhd
+++ b/hdl/vme64x-core/rtl/vme64x_pack.vhd
@@ -358,6 +358,7 @@ package vme64x_pack is
                                 DECIDE_NEXT_CYCLE,
                                 INCREMENT_ADDR,
                                 SET_DATA_PHASE
+--                           UGLY_WAIT_TO_MAKE_DECODING_WORK
                                        -- uncomment for using 2e modes:
 --                                  WAIT_FOR_DS_2e,
 --                                  ADDR_PHASE_1,
@@ -807,28 +808,27 @@ package vme64x_pack is
      );
  end component SingleRegInputSample;
+  component VME_IRQ_Controller
-  component VME_IRQ_Controller is
+    generic (
-    port(
+      g_retry_timeout : integer range 1024 to 16777215);
+    port (
      clk_i           : in  std_logic;
      reset_n_i       : in  std_logic;
      VME_IACKIN_n_i  : in  std_logic;
      VME_AS_n_i      : in  std_logic;
-      VME_AS1_n_i     : in  std_logic;
+      VME_DS_n_i      : in  std_logic_vector (1 downto 0);
-      VME_DS_n_i      : in  std_logic_vector(1 downto 0);
+      VME_ADDR_123_i  : in  std_logic_vector (2 downto 0);
-      VME_LWORD_n_i   : in  std_logic;
+      INT_Level_i     : in  std_logic_vector (7 downto 0);
-      VME_ADDR_123_i  : in  std_logic_vector(2 downto 0);
+      INT_Vector_i    : in  std_logic_vector (7 downto 0);
-      INT_Level_i     : in  std_logic_vector(7 downto 0);
-      INT_Vector_i    : in  std_logic_vector(7 downto 0);
      INT_Req_i       : in  std_logic;
-      VME_IRQ_n_o     : out std_logic_vector(6 downto 0);
+      VME_IRQ_n_o     : out std_logic_vector (6 downto 0);
      VME_IACKOUT_n_o : out std_logic;
      VME_DTACK_n_o   : out std_logic;
      VME_DTACK_OE_o  : out std_logic;
-      VME_DATA_o      : out std_logic_vector(31 downto 0);
+      VME_DATA_o      : out std_logic_vector (31 downto 0);
-      VME_DATA_DIR_o  : out std_logic
+      VME_DATA_DIR_o  : out std_logic);
-      );
+  end component;
-  end component VME_IRQ_Controller;
  component VME_CRAM is
    generic (dl : integer := 8;