Maintenance scheduled 24th July -- expect downtime along that day

Commit a120e226 authored by Tristan Gingold's avatar Tristan Gingold

Document inverted VME signal from V1 to V2.

parent 258f8f68
......@@ -426,6 +426,8 @@ Changes in V2 (compared to V1)
* WB data bus is 32 bit
* Internal component declarations removed.
* Async inputs registered with gc_sync_register.
* VME outputs `berr` and `irq` now follow the VME convention (they aren't
anymore inverted by the core).
[[appendix-implementation-of-the-core]]
Appendix: Implementation of the core
......
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