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VME64x core
Commit a994813b authored by Tristan Gingold's avatar Tristan Gingold
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vme64x_pkg: rename c_AM_A24_S to c_AM_A24

parent b9f87fb9
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hdl/rtl/vme64x_pkg.vhd
View file @ a994813b
...@@ -79,8 +79,8 @@ package vme64x_pkg is ...@@ -79,8 +79,8 @@ package vme64x_pkg is
-- Table 2.4 "Extended Address Modifier Code" page 12 2eSST -- Table 2.4 "Extended Address Modifier Code" page 12 2eSST
-- ANSI/VITA 1.5-2003(R2009) -- ANSI/VITA 1.5-2003(R2009)
subtype t_am_vec is std_logic_vector(5 downto 0); subtype t_am_vec is std_logic_vector(5 downto 0);
constant c_AM_A24_S_SUP : t_am_vec := "111101"; -- 0x3d constant c_AM_A24_SUP : t_am_vec := "111101"; -- 0x3d
constant c_AM_A24_S : t_am_vec := "111001"; -- 0x39 constant c_AM_A24 : t_am_vec := "111001"; -- 0x39
constant c_AM_A24_BLT : t_am_vec := "111011"; -- 0x3b constant c_AM_A24_BLT : t_am_vec := "111011"; -- 0x3b
constant c_AM_A24_BLT_SUP : t_am_vec := "111111"; -- 0x3f constant c_AM_A24_BLT_SUP : t_am_vec := "111111"; -- 0x3f
constant c_AM_A24_MBLT : t_am_vec := "111000"; -- 0x38 constant c_AM_A24_MBLT : t_am_vec := "111000"; -- 0x38
......
hdl/rtl/vme_bus.vhd
View file @ a994813b
...@@ -244,7 +244,7 @@ begin ...@@ -244,7 +244,7 @@ begin
-- Address modifier decoder -- Address modifier decoder
-- Both the supervisor and the user access modes are supported -- Both the supervisor and the user access modes are supported
with s_AMlatched select s_addressingType <= with s_AMlatched select s_addressingType <=
A24 when c_AM_A24_S_SUP | c_AM_A24_S, A24 when c_AM_A24_SUP | c_AM_A24,
A24_BLT when c_AM_A24_BLT | c_AM_A24_BLT_SUP, A24_BLT when c_AM_A24_BLT | c_AM_A24_BLT_SUP,
A24_MBLT when c_AM_A24_MBLT | c_AM_A24_MBLT_SUP, A24_MBLT when c_AM_A24_MBLT | c_AM_A24_MBLT_SUP,
CR_CSR when c_AM_CR_CSR, CR_CSR when c_AM_CR_CSR,
......
hdl/testbench/simple_tb/top_tb.vhd
View file @ a994813b
...@@ -1240,16 +1240,16 @@ begin ...@@ -1240,16 +1240,16 @@ begin
-- Set ADER -- Set ADER
write8_conf (x"7_ff73", x"00"); write8_conf (x"7_ff73", x"00");
write8_conf (x"7_ff77", x"20"); write8_conf (x"7_ff77", x"20");
write8_conf (x"7_ff7f", c_AM_A24_S & "00"); write8_conf (x"7_ff7f", c_AM_A24 & "00");
-- Enable card -- Enable card
write8_conf (x"7_fffb", b"0001_0000"); write8_conf (x"7_fffb", b"0001_0000");
read32 (x"00_20_00_10", c_AM_A24_S, d32); read32 (x"00_20_00_10", c_AM_A24, d32);
assert d32 = x"0000_0004" assert d32 = x"0000_0004"
report "incorrect read 32" severity error; report "incorrect read 32" severity error;
read32 (x"13_20_00_14", c_AM_A24_S, d32); read32 (x"13_20_00_14", c_AM_A24, d32);
assert d32 = x"0000_0500" assert d32 = x"0000_0500"
report "incorrect read 32" severity error; report "incorrect read 32" severity error;
...@@ -1259,12 +1259,12 @@ begin ...@@ -1259,12 +1259,12 @@ begin
-- Set ADER -- Set ADER
write8_conf (x"7_ff73", x"00"); write8_conf (x"7_ff73", x"00");
write8_conf (x"7_ff77", x"20"); write8_conf (x"7_ff77", x"20");
write8_conf (x"7_ff7f", c_AM_A24_S & "00"); write8_conf (x"7_ff7f", c_AM_A24 & "00");
-- Enable card -- Enable card
write8_conf (x"7_fffb", b"0001_0000"); write8_conf (x"7_fffb", b"0001_0000");
read32 (x"00_20_80_04", c_AM_A24_S, d32); read32 (x"00_20_80_04", c_AM_A24, d32);
assert d32 = (31 downto 0 => 'X') assert d32 = (31 downto 0 => 'X')
report "incorrect read 32" severity error; report "incorrect read 32" severity error;
...@@ -1349,7 +1349,7 @@ begin ...@@ -1349,7 +1349,7 @@ begin
end if; end if;
-- However, the A24 decoder is not enabled. -- However, the A24 decoder is not enabled.
read8 (x"56_00_00_00", c_AM_A24_S, d8); read8 (x"56_00_00_00", c_AM_A24, d8);
if g_SCENARIO = 8 then if g_SCENARIO = 8 then
assert d8 = "XXXXXXXX" report "unexpected reply (a24s)" severity error; assert d8 = "XXXXXXXX" report "unexpected reply (a24s)" severity error;
else else
......
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