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VME64x core
Commit e8b874db authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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parent 0f5490f0
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hdl/rtl/vme_bus.vhd
View file @ e8b874db
......@@ -68,30 +68,13 @@ entity vme_bus is
bridge_cpl_addr_dir_o : out std_logic;
bridge_cpl_data_dir_o : out std_logic;
-- VME signals
-- vme_as_n_i : in std_logic;
-- vme_lword_n_o : out std_logic := '0';
-- vme_lword_n_i : in std_logic;
-- vme_retry_n_o : out std_logic;
-- vme_retry_oe_o : out std_logic;
-- vme_write_n_i : in std_logic;
-- vme_ds_n_i : in std_logic_vector(1 downto 0);
-- vme_dtack_n_o : out std_logic;
-- vme_dtack_oe_o : out std_logic;
-- vme_berr_n_o : out std_logic;
-- vme_addr_i : in std_logic_vector(31 downto 1);
-- vme_addr_o : out std_logic_vector(31 downto 1) := (others => '0');
-- vme_addr_dir_o : out std_logic;
-- vme_addr_oe_n_o : out std_logic;
-- vme_data_i : in std_logic_vector(31 downto 0);
-- vme_data_o : out std_logic_vector(31 downto 0) := (others => '0');
-- vme_data_dir_o : out std_logic;
-- vme_data_oe_n_o : out std_logic;
-- vme_am_i : in std_logic_vector(5 downto 0);
-- vme_iackin_n_i : in std_logic;
-- vme_iack_n_i : in std_logic;
-- vme_iackout_n_o : out std_logic;
bridge_aux_valid_i : in std_logic;
bridge_aux_iack_n_i : in std_logic;
bridge_aux_iackin_n_i : in std_logic;
bridge_aux_iackout_n_o : out std_logic;
bridge_aux_irq_n_o : out std_logic_vector(7 downto 1);
-- WB signals
wb_stb_o : out std_logic;
wb_ack_i : in std_logic;
......@@ -180,8 +163,6 @@ architecture rtl of vme_bus is
-- Decoding ADDR and AM (selecting card or conf).
DECODE_ACCESS,
-- Wait until DS is asserted.
WAIT_FOR_DS,
-- Wait until DS is stable (and asserted).
LATCH_DS,
......@@ -208,10 +189,8 @@ architecture rtl of vme_bus is
IRQ_CHECK,
-- Pass IACKIN to IACKOUT
IRQ_PASS,
IRQ_PASS
-- Wait until AS is deasserted
WAIT_END
);
-- Main FSM signals
......@@ -243,10 +222,6 @@ begin
-- L | L | B to A L | L | B to Y
-- H | L |A to B, B to Y |
gen2: if g_BRIDGED_MODE = false generate
vme_data_oe_n_o <= '0'; -- Driven IFF DIR = 1
vme_addr_oe_n_o <= '0'; -- Driven IFF DIR = 1
end generate gen2;
------------------------------------------------------------------------------
-- Access Mode Decoders
......@@ -293,23 +268,15 @@ begin
variable addr_word_incr : natural range 0 to 7;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' or (g_BRIDGED_MODE = false and vme_as_n_i = '1') or ( g_BRIDGED_MODE = true and bridge_addr_req_i = '1') then
if rst_n_i = '0' or bridge_addr_req_i = '1' then
-- FSM reset after power up,
-- software reset, manually reset,
-- on rising edge of AS.
s_conf_req <= '0';
decode_start_o <= '0';
-- VME
vme_dtack_oe_o <= '0';
vme_dtack_n_o <= '1';
vme_data_dir_o <= '0';
vme_addr_dir_o <= '0';
vme_berr_n_o <= '1';
vme_addr_o <= (others => '0');
vme_lword_n_o <= '1';
vme_data_o <= (others => '0');
vme_iackout_n_o <= '1';
-- VME Bridge
s_dataPhase <= '0';
s_MBLT_Data <= '0';
s_mainFSMstate <= IDLE;
......@@ -320,16 +287,9 @@ begin
wb_stb_o <= '0';
s_err <= '0';
if g_BRIDGED_MODE = true and bridge_addr_req_i = '1' then
s_ADDRlatched <= bridge_addr_i;
s_LWORDlatched_n <= bridge_addr_lword_n_i;
s_AMlatched <= bridge_addr_am_i;
else
s_ADDRlatched <= (others => '0');
s_AMlatched <= (others => '0');
end if;
s_ADDRlatched <= bridge_addr_i;
s_LWORDlatched_n <= bridge_addr_lword_n_i;
s_AMlatched <= bridge_addr_am_i;
s_vme_addr_reg <= (others => '0');
s_vme_addr_dir <= '0';
......@@ -341,12 +301,6 @@ begin
else
s_conf_req <= '0';
decode_start_o <= '0';
vme_dtack_oe_o <= '0';
vme_dtack_n_o <= '1';
vme_data_dir_o <= '0';
vme_addr_dir_o <= '0';
vme_berr_n_o <= '1';
vme_iackout_n_o <= '1';
irq_ack_o <= '0';
bridge_write_ack_o <= '0';
......@@ -354,37 +308,24 @@ begin
case s_mainFSMstate is
when IDLE =>
-- Can only be here if vme_as_n_i has fallen to 0, which starts a
-- cycle.
if g_BRIDGED_MODE = false then
assert vme_as_n_i = '0';
end if;
-- Store ADDR, AM and LWORD
if g_BRIDGED_MODE = false then
s_ADDRlatched <= vme_addr_i;
s_LWORDlatched_n <= vme_lword_n_i;
s_AMlatched <= vme_am_i;
elsif bridge_addr_req_i = '1' then
if bridge_addr_req_i = '1' then
s_ADDRlatched <= bridge_addr_i;
s_LWORDlatched_n <= bridge_addr_lword_n_i;
s_AMlatched <= bridge_addr_am_i;
end if;
-- fixme: IACK handling in bridge mode
if g_BRIDGED_MODE = false then
if vme_iack_n_i = '1' then
-- ANSI/VITA 1-1994 Rule 2.11
-- Slaves MUST NOT respond to DTB cycles when IACK* is low.
s_mainFSMstate <= REFORMAT_ADDRESS;
else
-- IACK cycle.
s_mainFSMstate <= IRQ_CHECK;
end if;
else
if bridge_aux_iack_n_i = '1' and bridge_aux_valid_i = '1' then
-- ANSI/VITA 1-1994 Rule 2.11
-- Slaves MUST NOT respond to DTB cycles when IACK* is low.
s_mainFSMstate <= REFORMAT_ADDRESS;
else
-- IACK cycle.
s_mainFSMstate <= IRQ_CHECK;
end if;
when REFORMAT_ADDRESS =>
-- Reformat address according to the mode (A16, A24, A32)
-- FIXME: not needed if ADEM are correctly reduced to not compare
......@@ -415,14 +356,14 @@ begin
-- capability.
if s_LWORDlatched_n = '0' and s_ADDRlatched(1) = '1' then
-- unaligned.
s_mainFSMstate <= WAIT_END;
s_mainFSMstate <= IDLE;
else
if s_ADDRlatched(23 downto 19) = bar_i
and s_AMlatched = c_AM_CR_CSR
then
-- conf_sel = '1' it means CR/CSR space addressed
s_conf_sel <= '1';
s_mainFSMstate <= WAIT_FOR_DS;
s_mainFSMstate <= LATCH_DS;
else
s_mainFSMstate <= DECODE_ACCESS;
decode_start_o <= '1';
......@@ -433,18 +374,13 @@ begin
-- Check if this slave board is addressed.
-- Wait for DS in parallel.
if g_BRIDGED_MODE = true then
s_DS_latch_count <= (others => '0');
if bridge_write_req_i = '1' then
s_WRITElatched_n <= '0';
end if;
elsif vme_ds_n_i /= "11" then
s_WRITElatched_n <= vme_write_n_i;
if s_DS_latch_count /= 0 then
s_DS_latch_count <= s_DS_latch_count - 1;
end if;
if bridge_write_req_i = '1' then
s_WRITElatched_n <= bridge_write_write_n_i;
end if;
if bridge_read_req_i = '1' then
s_WRITElatched_n <= bridge_read_write_n_i;
end if;
if decode_done_i = '1' then
......@@ -454,90 +390,54 @@ begin
-- Keep only the local part of the address.
s_vme_addr_reg <= addr_decoder_i;
if g_BRIDGED_MODE = true then
if bridge_write_req_i = '1' then
end if;
elsif vme_ds_n_i = "11" then
s_mainFSMstate <= WAIT_FOR_DS;
else
s_mainFSMstate <= LATCH_DS;
end if;
s_mainFSMstate <= LATCH_DS;
else
-- Another board will answer; wait here the rising edge on
-- vme_as_i (done by top if).
s_mainFSMstate <= WAIT_END;
s_mainFSMstate <= IDLE;
end if;
else
-- Not yet decoded.
s_mainFSMstate <= DECODE_ACCESS;
end if;
when WAIT_FOR_DS =>
-- wait until DS /= "11"
-- Note: before entering this state, s_DS_latch_count must be set.
if g_BRIDGED_MODE then
if bridge_write_req_i = '1' or bridge_read_req_i = '1' THEN
s_mainFSMstate <= LATCH_DS;
if bridge_read_req_i = '1' then
s_WRITElatched_n <= '1';
else
s_WRITElatched_n <= bridge_write_write_n_i;
end if;
bridge_write_ack_o <= '1';
end if;
else
if vme_ds_n_i /= "11" then
-- ANSI/VITA 1-1994 Table 4-1
-- For interrupts ack, the handler MUST NOT drive WRITE* low
s_WRITElatched_n <= vme_write_n_i;
if s_DS_latch_count /= 0 then
s_DS_latch_count <= s_DS_latch_count - 1;
end if;
s_mainFSMstate <= LATCH_DS;
else
s_mainFSMstate <= WAIT_FOR_DS;
end if;
end if;
when LATCH_DS =>
-- This state is necessary indeed the VME master can assert the
-- DS lines not at the same time.
when LATCH_DS =>
if bridge_read_req_i = '1' THEN
s_WRITElatched_n <= bridge_read_write_n_i;
s_DSlatched_n <= bridge_read_ds_n_i;
bridge_read_ack_o <= '1';
end if;
-- ANSI/VITA 1-1994 Rule 2.53a
-- During all read cycles [...], the responding slave MUST NOT
-- drive the D[] lines until DSA* goes low.
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= '0';
if bridge_write_req_i = '1' then
s_locDataIn(63 downto 33) <= bridge_write_data_i(63 downto 33);
s_LWORDlatched_n <= bridge_write_data_i(32);
s_vme_data_reg <= bridge_write_data_i(31 downto 0);
s_WRITElatched_n <= bridge_write_write_n_i;
s_DSlatched_n <= bridge_write_ds_n_i;
bridge_write_ack_o <= '1';
end if;
-- This state is necessary indeed the VME master can assert the
-- DS lines not at the same time.
if s_transferType = MBLT then
s_dataPhase <= '1';
s
-- Start with D[31..0] when writing, but D[63..32] when reading.
s_vme_addr_reg(2) <= not s_WRITElatched_n;
else
s_dataPhase <= '0';
end if;
if g_BRIDGED_MODE then
if bridge_write_req_i = '1' then
s_locDataIn(63 downto 33) <= bridge_write_data_i(63 downto 33);
s_LWORDlatched_n <= bridge_write_data_i(32);
s_vme_data_reg <= bridge_write_data_i(31 downto 0);
s_DSlatched_n <= bridge_write_ds_n_i;
if bridge_write_req_i = '1' or bridge_read_req_i = '1' then
bridge_write_ack_o <= '1';
if s_irq_sel = '1' then
s_mainFSMstate <= DATA_TO_BUS;
elsif s_transferType = MBLT and s_MBLT_Data = '0' then
......@@ -548,39 +448,10 @@ s
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
end if;
end if;
else
if s_DS_latch_count = 0 or s_transferType = MBLT then
if s_irq_sel = '1' then
s_mainFSMstate <= DATA_TO_BUS;
elsif s_transferType = MBLT and s_MBLT_Data = '0' then
-- MBLT: ack address.
-- (Data are also read but discarded).
s_mainFSMstate <= DTACK_LOW;
else
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
end if;
-- Read DS (which is delayed to avoid metastability).
s_DSlatched_n <= vme_ds_n_i;
-- Read DATA (which are stable)
s_locDataIn(63 downto 33) <= vme_addr_i;
s_LWORDlatched_n <= vme_lword_n_i;
s_vme_data_reg <= vme_data_i;
else
s_mainFSMstate <= LATCH_DS;
s_DS_latch_count <= s_DS_latch_count - 1;
end if;
end if;
when CHECK_TRANSFER_TYPE =>
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= '0';
s_dataPhase <= s_dataPhase;
-- vme_addr is an output during MBLT *read* data transfer.
......@@ -618,7 +489,7 @@ s
-- capability.
if s_vme_lword_n_reg = '0' and s_DSlatched_n /= "00" then
-- unaligned.
s_mainFSMstate <= WAIT_END;
s_mainFSMstate <= IDLE;
else
s_mainFSMstate <= MEMORY_REQ;
s_conf_req <= s_conf_sel;
......@@ -632,9 +503,6 @@ s
when MEMORY_REQ =>
-- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_conf_req signal
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
-- Assert STB if stall was asserted.
wb_stb_o <= s_card_sel and wb_stall_i;
......@@ -707,7 +575,6 @@ s
end if;
when DATA_TO_BUS => -- entered upon successdful read or on s_irq_sel
if g_BRIDGED_MODE then
bridge_cpl_req_o <= '1';
bridge_cpl_data_dir_o <= s_WRITElatched_n or s_irq_sel;
......@@ -727,86 +594,44 @@ s
elsif s_transferType = SINGLE then
-- Cycle should be finished, but allow another access at
-- the same address (RMW).
s_mainFSMstate <= WAIT_FOR_DS;
s_mainFSMstate <= LATCH_DS;
else
if s_transferType = MBLT and s_MBLT_Data = '0' then
-- MBLT: end of address phase.
s_mainFSMstate <= WAIT_FOR_DS;
s_mainFSMstate <= LATCH_DS;
s_MBLT_Data <= '1';
else
-- Block
s_mainFSMstate <= INCREMENT_ADDR;
end if;
else
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
end if;
vme_addr_o <= s_locDataOut(63 downto 33);
vme_lword_n_o <= s_locDataOut(32);
vme_data_o <= s_locDataOut(31 downto 0);
-- ANSI/VITA 1-1994 Rule 2.54a
-- During all read cycles, the responding Slave MUST NOT drive
-- DTACK* low before it drives D[].
s_mainFSMstate <= DTACK_LOW;
end if;
when DTACK_LOW =>
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
-- Set DTACK (or retry or berr)
if s_card_sel = '1' and s_err = '1' then
vme_berr_n_o <= '0';
else
vme_dtack_n_o <= '0';
end if;
-- ANSI/VITA 1-1994 Rule 2.57
-- Once the responding Slave has driven DTACK* or BERR* low, it
-- MUST NOT release them or drive DTACK* high until it detects
-- both DS0* and DS1* high.
if vme_ds_n_i = "11" then
vme_data_dir_o <= '0';
vme_berr_n_o <= '1';
-- Rescind DTACK.
vme_dtack_n_o <= '1';
-- DS latch counter
s_DS_latch_count <= to_unsigned (c_num_latchDS, 3);
if s_irq_sel = '1' then
s_mainFSMstate <= WAIT_END;
elsif s_transferType = SINGLE then
-- Cycle should be finished, but allow another access at
-- the same address (RMW).
s_mainFSMstate <= WAIT_FOR_DS;
if s_irq_sel = '1' then
s_mainFSMstate <= IDLE;
elsif s_transferType = SINGLE then
-- Cycle should be finished, but allow another access at
-- the same address (RMW).
s_mainFSMstate <= LATCH_DS;
else
if s_transferType = MBLT and s_MBLT_Data = '0' then
-- MBLT: end of address phase.
s_mainFSMstate <= LATCH_DS;
s_MBLT_Data <= '1';
else
if s_transferType = MBLT and s_MBLT_Data = '0' then
-- MBLT: end of address phase.
s_mainFSMstate <= WAIT_FOR_DS;
s_MBLT_Data <= '1';
else
-- Block
s_mainFSMstate <= INCREMENT_ADDR;
end if;
-- Block
s_mainFSMstate <= INCREMENT_ADDR;
end if;
else
s_mainFSMstate <= DTACK_LOW;
end if;
when INCREMENT_ADDR =>
vme_dtack_oe_o <= '1';
vme_addr_dir_o <= s_vme_addr_dir;
if s_vme_lword_n_reg = '0' then
if s_transferType = MBLT then
......@@ -829,10 +654,10 @@ s
-- MBLT --> limit = 2048 bytes (rule 2.78 ANSI/VITA 1-1994)
s_vme_addr_reg (11 downto 1) <= std_logic_vector
(unsigned(s_vme_addr_reg (11 downto 1)) + addr_word_incr);
s_mainFSMstate <= WAIT_FOR_DS;
s_mainFSMstate <= LATCH_DS;
when IRQ_CHECK =>
if vme_iackin_n_i = '0' then
if bridge_aux_valid_i = '1' and bridge_aux_iackin_n_i = '0'then
if s_ADDRlatched(3 downto 1) = int_level_i
and irq_pending_i = '1'
then
......@@ -842,10 +667,12 @@ s
s_irq_sel <= '1';
irq_ack_o <= '1';
s_mainFSMstate <= WAIT_FOR_DS;
s_mainFSMstate <= LATCH_DS;
else
-- Pass
vme_iackout_n_o <= '0';
bridge_aux_iackout_n_o <= '0';
--vme_iackout_n_o <= '0';
s_mainFSMstate <= IRQ_PASS;
end if;
else
......@@ -854,26 +681,16 @@ s
when IRQ_PASS =>
-- Will stay here until AS is released.
vme_iackout_n_o <= '0';
bridge_aux_iackout_n_o <= '0';
--vme_iackout_n_o <= '0';
s_mainFSMstate <= IRQ_PASS;
when WAIT_END =>
-- Will stay here until AS is released.
s_mainFSMstate <= WAIT_END;
when others =>
-- No-op, wait until AS is released.
s_mainFSMstate <= WAIT_END;
end case;
end if;
end if;
end process;
-- Retry is not supported
vme_retry_n_o <= '1';
vme_retry_oe_o <= '0';
-- WB Master
with g_WB_GRANULARITY select
wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2) when WORD,
......
hdl/rtl/xvme64x_core.vhd
View file @ e8b874db
......@@ -266,6 +266,8 @@ architecture rtl of xvme64x_core is
signal b2b_aux_ga : std_logic_vector(5 downto 0);
signal b2b_aux_irq_n : std_logic_vector(7 downto 1);
signal b2b_aux_iackout_n : std_logic;
signal b2b_aux_iackin_n : std_logic;
signal b2b_aux_iack_n : std_logic;
-- List of supported AM.
constant c_AMCAP_ALLOWED : std_logic_vector(63 downto 0) :=
......@@ -399,7 +401,9 @@ begin
aux_valid_o => b2b_aux_valid,
aux_ga_o => b2b_aux_ga,
aux_irq_n_i => b2b_aux_irq_n,
aux_iackout_n_i => b2b_aux_iackout_n
aux_iackout_n_i => b2b_aux_iackout_n,
aux_iackin_n_o => b2b_aux_iackin_n,
aux_iack_n_o => b2b_aux_iack_n
);
end generate;
......@@ -436,30 +440,36 @@ begin
bridge_cpl_has_data_o => b2b_cpl_has_data,
bridge_cpl_dtack_n_o => b2b_cpl_dtack_n,
bridge_cpl_berr_o => b2b_cpl_berr,
bridge_aux_valid_i => b2b_aux_valid,
bridge_aux_iack_n_i => b2b_aux_iack_n,
bridge_aux_iackin_n_i => b2b_aux_iackin_n,
bridge_aux_iackout_n_o => b2b_aux_iackout_n,
-- VME
vme_as_n_i => s_vme_as_n,
vme_lword_n_o => vme_o.lword_n,
vme_lword_n_i => vme_i.lword_n,
vme_retry_n_o => vme_o.retry_n,
vme_retry_oe_o => vme_o.retry_oe,
vme_write_n_i => s_vme_write_n,
vme_ds_n_i => s_vme_ds_n,
vme_dtack_n_o => vme_o.dtack_n,
vme_dtack_oe_o => vme_o.dtack_oe,
vme_berr_n_o => s_vme_berr_n,
vme_addr_i => vme_i.addr,
vme_addr_o => vme_o.addr,
vme_addr_dir_o => vme_o.addr_dir,
vme_addr_oe_n_o => vme_o.addr_oe_n,
vme_data_i => vme_i.data,
vme_data_o => vme_o.data,
vme_data_dir_o => vme_o.data_dir,
vme_data_oe_n_o => vme_o.data_oe_n,
vme_am_i => vme_i.am,
vme_iackin_n_i => s_vme_iackin_n,
vme_iack_n_i => s_vme_iack_n,
vme_iackout_n_o => vme_o.iackout_n,
-- vme_as_n_i => s_vme_as_n,
-- vme_lword_n_o => vme_o.lword_n,
-- vme_lword_n_i => vme_i.lword_n,
-- vme_retry_n_o => vme_o.retry_n,
-- vme_retry_oe_o => vme_o.retry_oe,
-- vme_write_n_i => s_vme_write_n,
-- vme_ds_n_i => s_vme_ds_n,
-- vme_dtack_n_o => vme_o.dtack_n,
-- vme_dtack_oe_o => vme_o.dtack_oe,
-- vme_berr_n_o => s_vme_berr_n,
-- vme_addr_i => vme_i.addr,
-- vme_addr_o => vme_o.addr,
-- vme_addr_dir_o => vme_o.addr_dir,
-- vme_addr_oe_n_o => vme_o.addr_oe_n,
-- vme_data_i => vme_i.data,
-- vme_data_o => vme_o.data,
-- vme_data_dir_o => vme_o.data_dir,
-- vme_data_oe_n_o => vme_o.data_oe_n,
-- vme_am_i => vme_i.am,
-- vme_iackin_n_i => s_vme_iackin_n,
-- vme_iack_n_i => s_vme_iack_n,
-- vme_iackout_n_o => vme_o.iackout_n,
-- WB signals
wb_stb_o => wb_o.stb,
......
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