bugfix: VHDL code error in case() statement generation for <3 cases

git-svn-id: http://svn.ohwr.org/wishbone-gen@18 4537843c-45c2-4d80-8546-c3283569414f

bugfix: VHDL code error in case() statement generation for <3 cases
git-svn-id: http://svn.ohwr.org/wishbone-gen@18 4537843c-45c2-4d80-8546-c3283569414f
54091524 · twlostow · dcd6b1f9 · 54091524 · 54091524
Commit 54091524 authored Jun 18, 2010 by twlostow
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Showing with 8 additions and 3 deletions

cgen_vhdl.lua cgen_vhdl.lua +6 -1

wbgen2_fifo_sync.vhd lib/altera/wbgen2_fifo_sync.vhd +2 -2

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--- a/cgen_vhdl.lua
+++ b/cgen_vhdl.lua
@@ -19,6 +19,10 @@ fieldtype_2_vhdl[SLV] = "std_logic_vector";
 -- generates a string containing VHDL-compatible numeric constant of value [value] and size [numbits]
 function gen_vhdl_bin_literal(value, numbits)
+ if(numbits == 1) then
+	 return string.format("'%d'", csel(value==0,0,1));
+ end
    local str ='\"';
    local i,n,d,r;
@@ -352,7 +356,8 @@ function cgen_generate_vhdl_code(tree)
 			if(tsd.type == BIT) then 
 				return("'"..tss.name.."'");
 			elseif(tsd.type == SLV) then
-				return("std_logic_vector(to_unsigned("..tss.name..", "..calc_size(tsd).."))");
+--				return("std_logic_vector(to_unsigned("..tss.name..", "..calc_size(tsd).."))");
+					return gen_vhdl_bin_literal(tss.name, calc_size(tsd));
 			elseif(tsd.type == SIGNED) then
 				return("to_signed("..tss.name..", "..calc_size(tsd)..")");
 			elseif(tsd.type == UNSIGNED) then

--- a/lib/altera/wbgen2_fifo_sync.vhd
+++ b/lib/altera/wbgen2_fifo_sync.vhd
@@ -55,9 +55,9 @@ architecture rtl of wbgen2_fifo_sync is
      rdreq : in  std_logic;
      empty : out std_logic;
      clock : in  std_logic;
-      q     : out std_logic_vector (12 downto 0);
+      q     : out std_logic_vector (g_width-1 downto 0);
      wrreq : in  std_logic;
-      data  : in  std_logic_vector (12 downto 0);
+      data  : in  std_logic_vector (g_width-1 downto 0);
      full  : out std_logic
      );
  end component;