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Wishbone slave generator
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Wishbone slave generator
Commits
640e7b7a
Commit
640e7b7a
authored
Jul 03, 2017
by
Grzegorz Daniluk
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Merge branch 'greg-f_x_to_zero' into greg_proposed_master
parents
cc5a5c00
ed4e1500
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2 changed files
with
6 additions
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6 deletions
+6
-6
cgen_vhdl.lua
cgen_vhdl.lua
+3
-3
wbgen2
wbgen2
+3
-3
No files found.
cgen_vhdl.lua
View file @
640e7b7a
...
@@ -114,10 +114,10 @@ function cgen_vhdl_package()
...
@@ -114,10 +114,10 @@ function cgen_vhdl_package()
emit
(
"variable tmp: std_logic_vector(x'length-1 downto 0);"
);
emit
(
"variable tmp: std_logic_vector(x'length-1 downto 0);"
);
emit
(
"begin"
);
emit
(
"begin"
);
emit
(
"for i in 0 to x'length-1 loop"
);
emit
(
"for i in 0 to x'length-1 loop"
);
emit
(
"if
(x(i) = 'X' or x(i) = 'U')
then"
);
emit
(
"if
x(i) = '1'
then"
);
emit
(
"tmp(i):= '
0
';"
);
emit
(
"tmp(i):= '
1
';"
);
emit
(
"else"
);
emit
(
"else"
);
emit
(
"tmp(i):=
x(i)
;"
);
emit
(
"tmp(i):=
'0'
;"
);
emit
(
"end if; "
);
emit
(
"end if; "
);
emit
(
"end loop; "
);
emit
(
"end loop; "
);
emit
(
"return tmp;"
);
emit
(
"return tmp;"
);
...
...
wbgen2
View file @
640e7b7a
...
@@ -902,10 +902,10 @@ emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector is");
...
@@ -902,10 +902,10 @@ emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector is");
emit
(
"variable tmp: std_logic_vector(x'length-1 downto 0);"
);
emit
(
"variable tmp: std_logic_vector(x'length-1 downto 0);"
);
emit
(
"begin"
);
emit
(
"begin"
);
emit
(
"for i in 0 to x'length-1 loop"
);
emit
(
"for i in 0 to x'length-1 loop"
);
emit
(
"if
(x(i) = 'X' or x(i) = 'U')
then"
);
emit
(
"if
x(i) = '1'
then"
);
emit
(
"tmp(i):= '
0
';"
);
emit
(
"tmp(i):= '
1
';"
);
emit
(
"else"
);
emit
(
"else"
);
emit
(
"tmp(i):=
x(i)
;"
);
emit
(
"tmp(i):=
'0'
;"
);
emit
(
"end if; "
);
emit
(
"end if; "
);
emit
(
"end loop; "
);
emit
(
"end loop; "
);
emit
(
"return tmp;"
);
emit
(
"return tmp;"
);
...
...
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