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White Rabbit core collection
Commit 06fdd034 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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improved test inj_gen mode configuration (can be changed separately from other… 

improved test inj_gen mode configuration (can be changed separately from other config - different valid bit). This was convenient for software control implementation
parent 7f7f0255
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Showing with 56 additions and 31 deletions
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ 06fdd034
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Thu Jan 30 17:57:04 2014
-- Created : Fri Jan 31 09:58:14 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -37,8 +37,9 @@ package ep_wbgen2_pkg is
dmsr_ps_rdy_i : std_logic;
inj_ctrl_pic_conf_ifg_i : std_logic_vector(15 downto 0);
inj_ctrl_pic_conf_sel_i : std_logic_vector(2 downto 0);
inj_ctrl_pic_conf_mode_i : std_logic_vector(2 downto 0);
inj_ctrl_pic_conf_valid_i : std_logic;
inj_ctrl_pic_mode_id_i : std_logic_vector(2 downto 0);
inj_ctrl_pic_mode_valid_i : std_logic;
inj_ctrl_pic_ena_i : std_logic;
end record;
......@@ -60,8 +61,9 @@ package ep_wbgen2_pkg is
dmsr_ps_rdy_i => '0',
inj_ctrl_pic_conf_ifg_i => (others => '0'),
inj_ctrl_pic_conf_sel_i => (others => '0'),
inj_ctrl_pic_conf_mode_i => (others => '0'),
inj_ctrl_pic_conf_valid_i => '0',
inj_ctrl_pic_mode_id_i => (others => '0'),
inj_ctrl_pic_mode_valid_i => '0',
inj_ctrl_pic_ena_i => '0'
);
......@@ -126,10 +128,12 @@ package ep_wbgen2_pkg is
inj_ctrl_pic_conf_ifg_load_o : std_logic;
inj_ctrl_pic_conf_sel_o : std_logic_vector(2 downto 0);
inj_ctrl_pic_conf_sel_load_o : std_logic;
inj_ctrl_pic_conf_mode_o : std_logic_vector(2 downto 0);
inj_ctrl_pic_conf_mode_load_o : std_logic;
inj_ctrl_pic_conf_valid_o : std_logic;
inj_ctrl_pic_conf_valid_load_o : std_logic;
inj_ctrl_pic_mode_id_o : std_logic_vector(2 downto 0);
inj_ctrl_pic_mode_id_load_o : std_logic;
inj_ctrl_pic_mode_valid_o : std_logic;
inj_ctrl_pic_mode_valid_load_o : std_logic;
inj_ctrl_pic_ena_o : std_logic;
inj_ctrl_pic_ena_load_o : std_logic;
end record;
......@@ -193,10 +197,12 @@ package ep_wbgen2_pkg is
inj_ctrl_pic_conf_ifg_load_o => '0',
inj_ctrl_pic_conf_sel_o => (others => '0'),
inj_ctrl_pic_conf_sel_load_o => '0',
inj_ctrl_pic_conf_mode_o => (others => '0'),
inj_ctrl_pic_conf_mode_load_o => '0',
inj_ctrl_pic_conf_valid_o => '0',
inj_ctrl_pic_conf_valid_load_o => '0',
inj_ctrl_pic_mode_id_o => (others => '0'),
inj_ctrl_pic_mode_id_load_o => '0',
inj_ctrl_pic_mode_valid_o => '0',
inj_ctrl_pic_mode_valid_load_o => '0',
inj_ctrl_pic_ena_o => '0',
inj_ctrl_pic_ena_load_o => '0'
);
......@@ -246,8 +252,9 @@ tmp.dmsr_ps_val_i := f_x_to_zero(left.dmsr_ps_val_i) or f_x_to_zero(right.dmsr_p
tmp.dmsr_ps_rdy_i := f_x_to_zero(left.dmsr_ps_rdy_i) or f_x_to_zero(right.dmsr_ps_rdy_i);
tmp.inj_ctrl_pic_conf_ifg_i := f_x_to_zero(left.inj_ctrl_pic_conf_ifg_i) or f_x_to_zero(right.inj_ctrl_pic_conf_ifg_i);
tmp.inj_ctrl_pic_conf_sel_i := f_x_to_zero(left.inj_ctrl_pic_conf_sel_i) or f_x_to_zero(right.inj_ctrl_pic_conf_sel_i);
tmp.inj_ctrl_pic_conf_mode_i := f_x_to_zero(left.inj_ctrl_pic_conf_mode_i) or f_x_to_zero(right.inj_ctrl_pic_conf_mode_i);
tmp.inj_ctrl_pic_conf_valid_i := f_x_to_zero(left.inj_ctrl_pic_conf_valid_i) or f_x_to_zero(right.inj_ctrl_pic_conf_valid_i);
tmp.inj_ctrl_pic_mode_id_i := f_x_to_zero(left.inj_ctrl_pic_mode_id_i) or f_x_to_zero(right.inj_ctrl_pic_mode_id_i);
tmp.inj_ctrl_pic_mode_valid_i := f_x_to_zero(left.inj_ctrl_pic_mode_valid_i) or f_x_to_zero(right.inj_ctrl_pic_mode_valid_i);
tmp.inj_ctrl_pic_ena_i := f_x_to_zero(left.inj_ctrl_pic_ena_i) or f_x_to_zero(right.inj_ctrl_pic_ena_i);
return tmp;
end function;
......
modules/wr_endpoint/ep_tx_inject_ctrl.vhd
View file @ 06fdd034
......@@ -133,16 +133,18 @@ begin -- rtl
if_gap_value <= (others=>'0');
pck_sel <= (others=>'0');
gen_ena <= '0';
inj_mode <= (others=>'0');
else
if(regs_i.inj_ctrl_pic_ena_load_o = '1') then -- writing the register
if (regs_i.inj_ctrl_pic_conf_valid_o = '1') then
if_gap_value <= unsigned(regs_i.inj_ctrl_pic_conf_ifg_o);
pck_sel <= regs_i.inj_ctrl_pic_conf_sel_o;
inj_mode <= regs_i.inj_ctrl_pic_conf_mode_o(1 downto 0);
end if;
if(regs_i.inj_ctrl_pic_mode_valid_o = '1') then
inj_mode <= regs_i.inj_ctrl_pic_mode_id_o(1 downto 0);
end if;
gen_ena <= regs_i.inj_ctrl_pic_ena_o;
end if;
end if;
end if;
end process;
......@@ -227,6 +229,6 @@ begin -- rtl
regs_o.inj_ctrl_pic_conf_sel_i <= pck_sel;
regs_o.inj_ctrl_pic_conf_valid_i <= '0';
regs_o.inj_ctrl_pic_ena_i <= gen_ena;
regs_o.inj_ctrl_pic_conf_mode_i<= '0' & inj_mode;
regs_o.inj_ctrl_pic_mode_id_i <= '0' & inj_mode;
end rtl;
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ 06fdd034
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Thu Jan 30 17:57:04 2014
-- Created : Fri Jan 31 09:58:14 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -153,8 +153,9 @@ begin
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
regs_o.inj_ctrl_pic_conf_mode_load_o <= '0';
regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
regs_o.inj_ctrl_pic_ena_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -177,8 +178,9 @@ begin
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
regs_o.inj_ctrl_pic_conf_mode_load_o <= '0';
regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
regs_o.inj_ctrl_pic_ena_load_o <= '0';
ack_in_progress <= '0';
else
......@@ -200,8 +202,9 @@ begin
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.inj_ctrl_pic_conf_ifg_load_o <= '0';
regs_o.inj_ctrl_pic_conf_sel_load_o <= '0';
regs_o.inj_ctrl_pic_conf_mode_load_o <= '0';
regs_o.inj_ctrl_pic_conf_valid_load_o <= '0';
regs_o.inj_ctrl_pic_mode_id_load_o <= '0';
regs_o.inj_ctrl_pic_mode_valid_load_o <= '0';
regs_o.inj_ctrl_pic_ena_load_o <= '0';
end if;
else
......@@ -661,16 +664,17 @@ begin
if (wb_we_i = '1') then
regs_o.inj_ctrl_pic_conf_ifg_load_o <= '1';
regs_o.inj_ctrl_pic_conf_sel_load_o <= '1';
regs_o.inj_ctrl_pic_conf_mode_load_o <= '1';
regs_o.inj_ctrl_pic_conf_valid_load_o <= '1';
regs_o.inj_ctrl_pic_mode_id_load_o <= '1';
regs_o.inj_ctrl_pic_mode_valid_load_o <= '1';
regs_o.inj_ctrl_pic_ena_load_o <= '1';
end if;
rddata_reg(15 downto 0) <= regs_i.inj_ctrl_pic_conf_ifg_i;
rddata_reg(18 downto 16) <= regs_i.inj_ctrl_pic_conf_sel_i;
rddata_reg(22 downto 20) <= regs_i.inj_ctrl_pic_conf_mode_i;
rddata_reg(23) <= regs_i.inj_ctrl_pic_conf_valid_i;
rddata_reg(19) <= regs_i.inj_ctrl_pic_conf_valid_i;
rddata_reg(22 downto 20) <= regs_i.inj_ctrl_pic_mode_id_i;
rddata_reg(23) <= regs_i.inj_ctrl_pic_mode_valid_i;
rddata_reg(24) <= regs_i.inj_ctrl_pic_ena_i;
rddata_reg(19) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -852,10 +856,12 @@ begin
regs_o.inj_ctrl_pic_conf_ifg_o <= wrdata_reg(15 downto 0);
-- Config: packet pattern sel id
regs_o.inj_ctrl_pic_conf_sel_o <= wrdata_reg(18 downto 16);
-- Config: packet generate mode
regs_o.inj_ctrl_pic_conf_mode_o <= wrdata_reg(22 downto 20);
-- Config: valid
regs_o.inj_ctrl_pic_conf_valid_o <= wrdata_reg(23);
regs_o.inj_ctrl_pic_conf_valid_o <= wrdata_reg(19);
-- Mode: packet generate mode
regs_o.inj_ctrl_pic_mode_id_o <= wrdata_reg(22 downto 20);
-- Mode: valid
regs_o.inj_ctrl_pic_mode_valid_o <= wrdata_reg(23);
-- Frame Generation Enabled
regs_o.inj_ctrl_pic_ena_o <= wrdata_reg(24);
rwaddr_reg <= wb_adr_i;
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ 06fdd034
......@@ -689,10 +689,17 @@ peripheral {
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Config: packet generate mode";
prefix = "PIC_CONF_MODE";
name = "Config: valid";
prefix = "PIC_CONF_VALID";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Mode: packet generate mode";
prefix = "PIC_MODE_ID";
size = 3;
type = SLV;
align= 4;
......@@ -702,13 +709,14 @@ peripheral {
};
field {
name = "Config: valid";
prefix = "PIC_CONF_VALID";
name = "Mode: valid";
prefix = "PIC_MODE_VALID";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Frame Generation Enabled";
prefix = "PIC_ENA";
......
sim/endpoint_regs.v
View file @ 06fdd034
......@@ -120,9 +120,11 @@
`define EP_INJ_CTRL_PIC_CONF_IFG 32'h0000ffff
`define EP_INJ_CTRL_PIC_CONF_SEL_OFFSET 16
`define EP_INJ_CTRL_PIC_CONF_SEL 32'h00070000
`define EP_INJ_CTRL_PIC_CONF_MODE_OFFSET 20
`define EP_INJ_CTRL_PIC_CONF_MODE 32'h00700000
`define EP_INJ_CTRL_PIC_CONF_VALID_OFFSET 23
`define EP_INJ_CTRL_PIC_CONF_VALID 32'h00800000
`define EP_INJ_CTRL_PIC_CONF_VALID_OFFSET 19
`define EP_INJ_CTRL_PIC_CONF_VALID 32'h00080000
`define EP_INJ_CTRL_PIC_MODE_ID_OFFSET 20
`define EP_INJ_CTRL_PIC_MODE_ID 32'h00700000
`define EP_INJ_CTRL_PIC_MODE_VALID_OFFSET 23
`define EP_INJ_CTRL_PIC_MODE_VALID 32'h00800000
`define EP_INJ_CTRL_PIC_ENA_OFFSET 24
`define EP_INJ_CTRL_PIC_ENA 32'h01000000
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