added pin for bus powered onewire devices

0d0ee9b1 · Stefan Rauch · Wesley W. Terpstra · d8027727 · 0d0ee9b1 · 0d0ee9b1
Commit 0d0ee9b1 authored Jul 03, 2012 by Stefan Rauch Committed by Wesley W. Terpstra Jul 03, 2012
Showing with 8 additions and 0 deletions

wr_core.vhd modules/wrc_core/wr_core.vhd +2 -0

wrc_periph.vhd modules/wrc_core/wrc_periph.vhd +2 -0

wrcore_pkg.vhd modules/wrc_core/wrcore_pkg.vhd +1 -0

xwr_core.vhd modules/wrc_core/xwr_core.vhd +3 -0

No files found.
--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -153,6 +153,7 @@ entity wr_core is
    -----------------------------------------
    -- 1-wire
    -----------------------------------------
+    owr_pwren_o: out std_logic_vector(1 downto 0);
    owr_en_o : out std_logic_vector(1 downto 0);
    owr_i    : in  std_logic_vector(1 downto 0);

@@ -719,6 +720,7 @@ begin
      uart_rxd_i => uart_rxd_i,
      uart_txd_o => uart_txd_o,

+      owr_pwren_o => owr_pwren_o,
      owr_en_o => owr_en_o,
      owr_i    => owr_i
      );

--- a/modules/wrc_core/wrc_periph.vhd
+++ b/modules/wrc_core/wrc_periph.vhd
@@ -67,6 +67,7 @@ entity wrc_periph is
    uart_txd_o : out std_logic;

    -- 1-Wire
+    owr_pwren_o: out std_logic_vector(1 downto 0);
    owr_en_o : out std_logic_vector(1 downto 0);
    owr_i    : in  std_logic_vector(1 downto 0)
    );
@@ -322,6 +323,7 @@ begin
      slave_o => slave_o(2),
      desc_o  => open,

+      owr_pwren_o => owr_pwren_o,
      owr_en_o => owr_en_o,
      owr_i    => owr_i
      );

--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -219,6 +219,7 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
      slave_o     : out t_wishbone_slave_out_array(0 to 2);
      uart_rxd_i  : in  std_logic;
      uart_txd_o  : out std_logic;
+      owr_pwren_o : out std_logic_vector(1 downto 0);
      owr_en_o    : out std_logic_vector(1 downto 0);
      owr_i       : in  std_logic_vector(1 downto 0)
      );

--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -134,6 +134,7 @@ entity xwr_core is
    -----------------------------------------
    -- 1-wire
    -----------------------------------------
+    owr_pwren_o: out std_logic_vector(1 downto 0);
    owr_en_o : out std_logic_vector(1 downto 0);
    owr_i    : in  std_logic_vector(1 downto 0);

@@ -245,6 +246,7 @@ architecture struct of xwr_core is
      uart_rxd_i : in  std_logic;
      uart_txd_o : out std_logic;

+      owr_pwren_o: out std_logic_vector(1 downto 0);
      owr_en_o : out std_logic_vector(1 downto 0);
      owr_i    : in  std_logic_vector(1 downto 0);

@@ -372,6 +374,7 @@ begin
      uart_rxd_i  => uart_rxd_i,
      uart_txd_o  => uart_txd_o,

+      owr_pwren_o => owr_pwren_o,
      owr_en_o => owr_en_o,
      owr_i    => owr_i,