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White Rabbit core collection
Commit 0e860314 authored by Stefan Rauch's avatar Stefan Rauch Committed by Wesley W. Terpstra
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Move component definitions into packages 

Update the SCU usage of the wrcore (and attached SFP)
Move the pow_reset and flash_loader into altera platform components
parent 1b373238
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Showing with 405 additions and 755 deletions
modules/lpc_uart/Manifest.py
View file @ 0e860314
files = [
"lpc_peripheral.vhd",
"lpc_uart.vhd",
"lpc_uart_pkg.vhd",
"postcode.vhd",
"serirq_defines.v",
"serirq_slave.v"
......
modules/lpc_uart/lpc_uart_pkg.vhd 0 → 100644
View file @ 0e860314
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
package lpc_uart_pkg is
component lpc_uart is
port (
lpc_clk: in std_logic;
lpc_serirq: inout std_logic;
lpc_ad: inout std_logic_vector(3 downto 0);
lpc_frame_n: in std_logic;
lpc_reset_n: in std_logic;
serial_rxd: in std_logic;
serial_txd: out std_logic;
serial_dtr: out std_logic;
serial_dcd: in std_logic;
serial_dsr: in std_logic;
serial_ri: in std_logic;
serial_cts: in std_logic;
serial_rts: out std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end component;
end lpc_uart_pkg;
modules/wrc_core/wr_core.vhd
View file @ 0e860314
......@@ -153,9 +153,9 @@ entity wr_core is
-----------------------------------------
-- 1-wire
-----------------------------------------
owr_pwren_o: out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
-----------------------------------------
--External WB interface
......@@ -410,7 +410,9 @@ architecture struct of wr_core is
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_sel : std_logic_vector(3 downto 0);
signal dac_dpll_load_p1 : std_logic;
signal clk_fb : std_logic_vector(g_aux_clks downto 0);
signal out_enable : std_logic_vector(g_aux_clks downto 0);
--component chipscope_ila
-- port (
......@@ -497,8 +499,7 @@ begin
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i(0) => phy_rx_rbclk_i,
-- Feedback clocks (i.e. the outputs of the main or aux oscillator)
clk_fb_i(0) => clk_ref_i,
clk_fb_i(1) => clk_aux_i(0),
clk_fb_i => clk_fb,
-- DMTD Offset clock
clk_dmtd_i => clk_dmtd_i,
......@@ -515,8 +516,7 @@ begin
dac_out_sel_o => dac_dpll_sel, --for now use only one output
dac_out_load_o => dac_dpll_load_p1,
out_enable_i(0) => '1',
out_enable_i(1) => tm_clk_aux_lock_en_i,
out_enable_i => out_enable,
out_locked_o => spll_out_locked,
......@@ -526,13 +526,20 @@ begin
debug_o => dio_o
);
clk_fb(0) <= clk_ref_i;
clk_fb(g_aux_clks downto 1) <= clk_aux_i;
out_enable(0) <= '1';
out_enable(g_aux_clks downto 1) <= (others => tm_clk_aux_lock_en_i);
dac_dpll_data_o <= dac_dpll_data;
dac_dpll_load_p1_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel= x"0") else '0';
tm_dac_value_o <= x"00" & dac_dpll_data;
tm_dac_wr_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"1") else '0';
tm_clk_aux_locked_o <= spll_out_locked(1);
locked_spll : if g_aux_clks > 0 generate
tm_clk_aux_locked_o <= spll_out_locked(1); -- !!! what if more than one clock?! FIXME
end generate;
softpll_irq <= spll_wb_out.int;
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 0e860314
......@@ -307,4 +307,114 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
);
end component;
-----------------------------------------------------------------------------
-- Public WR component definitions
-----------------------------------------------------------------------------
component xwr_core is
generic(
g_simulation : integer := 0;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 20480; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
tm_link_up_o : out std_logic;
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic;
link_ok_o : out std_logic
);
end component;
component spec_serial_dac_arb
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component;
end wrcore_pkg;
modules/wrc_core/xwr_core.vhd
View file @ 0e860314
......@@ -326,6 +326,7 @@ begin
g_virtual_uart => g_virtual_uart,
g_rx_buffer_size => g_ep_rxbuf_size,
g_with_external_clock_input => g_with_external_clock_input,
g_aux_clks => g_aux_clks,
g_dpram_initf => g_dpram_initf,
g_dpram_initv => g_dpram_initv,
g_dpram_size => g_dpram_size,
......
platform/altera/Manifest.py
View file @ 0e860314
files = [ "altera_pkg.vhd", "flash_loader.vhd", "pow_reset.vhd" ]
modules = {"local":"wr_gxb_phy_arria2"}
\ No newline at end of file
platform/altera/altera_pkg.vhd 0 → 100644
View file @ 0e860314
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
package wr_altera_pkg is
component flash_loader
port (
noe_in : in std_logic
);
end component;
component pow_reset is
port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
);
end component;
component dmtd_clk_pll
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component;
component sys_pll
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic;
c1 : out std_logic;
locked : out std_logic
);
end component;
component wr_gxb_phy_arriaii
generic (
g_simulation : integer;
g_force_disparity : integer);
port (
clk_reconf_i : in std_logic;
clk_ref_i : in std_logic;
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic;
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
end wr_altera_pkg;
platform/xilinx/Manifest.py
View file @ 0e860314
files = [ "wr_xilinx_pkg.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file
platform/xilinx/wr_xilinx_pkg.vhd 0 → 100644
View file @ 0e860314
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
package wr_xilinx_pkg is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer;
g_ch0_use_refclk_out : boolean := false;
g_ch1_use_refclk_out : boolean := false);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
end wr_xilinx_pkg;
syn/gsi_scu/wr_core_demo/scu.qsf
View file @ 0e860314
......@@ -704,6 +704,9 @@ set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 3.47P -to DDR3
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.66N -to DDR3_ODT
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 3.47P -to DDR3_ODT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR3_WE_n
set_global_assignment -name VHDL_FILE ../../../platform/altera/pow_reset.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/flash_loader.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/altera_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_dacs/spec_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_dacs/spec_serial_dac_arb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_receiver.vhd
......@@ -721,6 +724,7 @@ set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_transmitter.vhd
set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v
set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/postcode.vhd
set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart.vhd
set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_peripheral.vhd
set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_slave.v
set_global_assignment -name VERILOG_FILE ../../../platform/altera/ddr3/alt_jtagavalon.v
......@@ -739,12 +743,10 @@ set_global_assignment -name VHDL_FILE ../../../modules/wr_eca/xwr_eca.vhd
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/flash_loader.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_tlu/wb_timestamp_latch.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_tlu/wb_cores_pkg_gsi.vhd
set_global_assignment -name SDC_FILE ../../../top/gsi_scu/wr_core_demo/scu_top.sdc
set_global_assignment -name VHDL_FILE ../../../modules/fabric/wr_fabric_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_scu/wr_core_demo/pow_reset.vhd
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../../modules/fabric/xwb_fabric_source.vhd
......
syn/gsi_scu2/wr_core_demo/scu2.qsf
View file @ 0e860314
......@@ -1101,6 +1101,9 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLE
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name VHDL_FILE ../../../platform/altera/pow_reset.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/flash_loader.vhd
set_global_assignment -name VHDL_FILE ../../../platform/altera/altera_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_dacs/spec_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_dacs/spec_serial_dac_arb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/uart/uart_transmitter.vhd
......@@ -1119,6 +1122,7 @@ set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_slave.
set_global_assignment -name VERILOG_FILE ../../../modules/lpc_uart/serirq_defines.v
set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/postcode.vhd
set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart.vhd
set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_uart_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/lpc_uart/lpc_peripheral.vhd
set_global_assignment -name VERILOG_FILE ../../../platform/altera/ddr3/alt_jtagavalon.v
set_global_assignment -name TCL_SCRIPT_FILE ../../../platform/altera/ddr3/ddr3_mem_pin_assignments.tcl
......
top/gsi_scu/wr_core_demo/scu_top.vhd
View file @ 0e860314
This diff is collapsed.
top/gsi_scu2/wr_core_demo/flash_loader.vhd deleted 100644 → 0
View file @ 1b373238
-- megafunction wizard: %Serial Flash Loader%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altserial_flash_loader
-- ============================================================
-- File Name: flash_loader.vhd
-- Megafunction Name(s):
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY flash_loader IS
PORT
(
noe_in : IN STD_LOGIC
);
END flash_loader;
ARCHITECTURE SYN OF flash_loader IS
COMPONENT altserial_flash_loader
GENERIC (
enable_quad_spi_support : NATURAL;
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_quad_spi_support => 0,
enable_shared_access => "OFF",
enhanced_mode => 1,
intended_device_family => "Arria II GX",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
top/gsi_scu2/wr_core_demo/pow_reset.vhd deleted 100644 → 0
View file @ 1b373238
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pow_reset is
port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
);
end entity;
architecture pow_reset_arch of pow_reset is
signal powerOn : unsigned(6 downto 0) := "0000000"; -- 7Bit for 1ms nrst
begin
nres : process(Clk)
begin
if Clk'event and Clk = '1' then
if nreset = '0' then
powerOn <= powerOn + 1;
end if;
nReset <= std_logic(powerOn(powerON'high));
end if;
end process;
end architecture;
top/gsi_scu2/wr_core_demo/scu_top.vhd
View file @ 0e860314
This diff is collapsed.
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 0e860314
......@@ -230,150 +230,6 @@ architecture rtl of spec_top is
);
end component; -- gn4124_core
component xwr_core is
generic(
g_simulation : integer := 0;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_size : integer := 20480; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
led_red_o : out std_logic;
led_green_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic
);
end component;
component wr_gtp_phy_spartan6
generic (
g_simulation : integer;
g_ch0_use_refclk_out : boolean := false;
g_ch1_use_refclk_out : boolean := false);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
component spec_serial_dac_arb
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component;
--component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
......
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