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White Rabbit core collection
Commits
10ccc8c1
Commit
10ccc8c1
authored
Jan 20, 2017
by
Grzegorz Daniluk
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update testbeches Manifests to use new hdlmake
parent
486137e9
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7 changed files
with
69 additions
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10 deletions
+69
-10
Manifest.py
testbench/top_level/Manifest.py
+7
-0
Manifest.py
testbench/wr_endpoint/full_tb/Manifest.py
+7
-0
Manifest.py
testbench/wr_fabric_reg/Manifest.py
+20
-0
Manifest.py
testbench/wr_minic/Manifest.py
+7
-5
Manifest.py
testbench/wrc_core/main_tb/Manifest.py
+9
-1
Manifest.py
testbench/xwrf_loopback/Manifest.py
+7
-0
Manifest.py
testbench/xwrf_mux/Manifest.py
+12
-4
No files found.
testbench/top_level/Manifest.py
View file @
10ccc8c1
action
=
"simulation"
target
=
"xilinx"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
sim_tool
=
"modelsim"
top_module
=
"main"
fetchto
=
"../../ip_cores"
vlog_opt
=
"+incdir+../../sim +incdir+gn4124_bfm"
include_dirs
=
[
"../../sim"
,
"gn4124_bfm"
]
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../.."
,
...
...
testbench/wr_endpoint/full_tb/Manifest.py
View file @
10ccc8c1
target
=
"xilinx"
action
=
"simulation"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
sim_tool
=
"modelsim"
top_module
=
"main"
files
=
"main.sv"
fetchto
=
"../../../ip_cores"
vlog_opt
=
"+incdir+../../../sim +incdir+../../../sim/fabric_emu"
include_dirs
=
[
"../../../sim"
]
modules
=
{
"git"
:
[
"git@ohwr.org:hdl-core-lib/general-cores.git"
],
"local"
:
[
"../../../modules/wr_endpoint"
,
"../../../modules/timing"
,
...
...
testbench/wr_fabric_reg/Manifest.py
0 → 100644
View file @
10ccc8c1
action
=
"simulation"
files
=
"main.sv"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
sim_tool
=
"modelsim"
top_module
=
"main"
fetchto
=
"../../ip_cores"
target
=
"xilinx"
vlog_opt
=
"+incdir+../../sim"
include_dirs
=
[
"../../sim"
]
modules
=
{
"local"
:
[
"../../"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/etherbone-core"
,
"../../ip_cores/gn4124-core"
]}
testbench/wr_minic/Manifest.py
View file @
10ccc8c1
action
=
"simulation"
target
=
"xilinx"
#
syn_device = "xc6slx45t"
#
syn_grade = "-3"
#
syn_package = "fgg484"
#
sim_tool = "modelsim"
#
top_module = "main"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
sim_tool
=
"modelsim"
top_module
=
"main"
fetchto
=
"../../ip_cores"
vlog_opt
=
"+incdir+../../sim"
include_dirs
=
[
"../../sim"
]
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../../"
,
...
...
testbench/wrc_core/main_tb/Manifest.py
View file @
10ccc8c1
action
=
"simulation"
target
=
"xilinx"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
sim_tool
=
"modelsim"
top_module
=
"main"
fetchto
=
"../../../ip_cores"
vlog_opt
=
"+incdir+../../../sim"
files
=
[
"main.sv"
]
include_dirs
=
[
"../../../sim"
]
modules
=
{
"local"
:
[
"../../.."
,
"../../../modules/fabric"
,
"../../../ip_cores/general-cores"
,
"../../../ip_cores/etherbone-core"
,
"../../../ip_cores/gn4124-core"
]}
"../../../ip_cores/gn4124-core"
,
"../../../ip_cores/urv-core"
]}
testbench/xwrf_loopback/Manifest.py
View file @
10ccc8c1
action
=
"simulation"
target
=
"xilinx"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
sim_tool
=
"modelsim"
top_module
=
"main"
fetchto
=
"../../ip_cores"
vlog_opt
=
"+incdir+../../sim"
include_dirs
=
[
"../../sim"
]
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../.."
,
...
...
testbench/xwrf_mux/Manifest.py
View file @
10ccc8c1
action
=
"simulation"
target
=
"xilinx"
files
=
"main.sv"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
sim_tool
=
"modelsim"
top_module
=
"main"
fetchto
=
"../../ip_cores"
target
=
"xilinx"
vlog_opt
=
"+incdir+../../sim"
modules
=
{
"local"
:
"../../"
}
include_dirs
=
[
"../../sim"
]
modules
=
{
"local"
:
[
"../../"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/etherbone-core"
,
"../../ip_cores/gn4124-core"
]}
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