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White Rabbit core collection
Commit 1983dde2 authored by A. Hahn's avatar A. Hahn
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arria10: e3p1 -> updated atx_pll and cmu_pll and phy

parent d45e32f4
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platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/synth/wr_arria10_e3p1_atx_pll.v
View file @ 1983dde2
......@@ -11,7 +11,7 @@ module wr_arria10_e3p1_atx_pll (
output wire tx_serial_clk // tx_serial_clk.clk
);
wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_chk6tua #(
wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua #(
.enable_pll_reconfig (0),
.rcfg_jtag_enable (0),
.rcfg_separate_avmm_busy (0),
......@@ -60,7 +60,7 @@ module wr_arria10_e3p1_atx_pll (
.atx_pll_dsm_fractional_value_ready ("pll_k_ready"),
.atx_pll_iqclk_mux_sel ("iqtxrxclk0"),
.atx_pll_vco_bypass_enable ("false"),
.atx_pll_l_counter (16),
.atx_pll_l_counter (4),
.atx_pll_l_counter_enable ("true"),
.atx_pll_cascadeclk_test ("cascadetest_off"),
.atx_pll_hclk_divide (1),
......@@ -68,11 +68,11 @@ module wr_arria10_e3p1_atx_pll (
.atx_pll_m_counter (40),
.atx_pll_ref_clk_div (1),
.atx_pll_bw_sel ("medium"),
.atx_pll_datarate ("1250000000 bps"),
.atx_pll_datarate ("5000000000 bps"),
.atx_pll_device_variant ("device1"),
.atx_pll_initial_settings ("true"),
.atx_pll_lc_mode ("lccmu_normal"),
.atx_pll_output_clock_frequency ("625000000 Hz"),
.atx_pll_output_clock_frequency ("2500000000 Hz"),
.atx_pll_powerdown_mode ("powerup"),
.atx_pll_prot_mode ("basic_tx"),
.atx_pll_reference_clock_frequency ("125000000 Hz"),
......@@ -99,7 +99,7 @@ module wr_arria10_e3p1_atx_pll (
.hssi_pma_cgb_master_x1_div_m_sel ("divbypass"),
.hssi_pma_cgb_master_cgb_enable_iqtxrxclk ("disable_iqtxrxclk"),
.hssi_pma_cgb_master_ser_mode ("sixty_four_bit"),
.hssi_pma_cgb_master_datarate ("1250000000 bps"),
.hssi_pma_cgb_master_datarate ("5000000000 bps"),
.hssi_pma_cgb_master_cgb_power_down ("normal_cgb"),
.hssi_pma_cgb_master_observe_cgb_clocks ("observe_nothing"),
.hssi_pma_cgb_master_op_mode ("enabled"),
......
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_atx_pll/wr_arria10_e3p1_atx_pll/synth/wr_arria10_e3p1_atx_pll_cfg.v
View file @ 1983dde2
config wr_arria10_e3p1_atx_pll_cfg;
design wr_arria10_e3p1_atx_pll;
instance wr_arria10_e3p1_atx_pll.xcvr_atx_pll_a10_0 use wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_chk6tua;
instance wr_arria10_e3p1_atx_pll.xcvr_atx_pll_a10_0 use wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181.wr_arria10_e3p1_atx_pll_altera_xcvr_atx_pll_a10_181_z7ksuua;
endconfig
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/synth/wr_arria10_e3p1_cmu_pll.v 0 → 100644
View file @ 1983dde2
// wr_arria10_e3p1_cmu_pll.v
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module wr_arria10_e3p1_cmu_pll (
output wire pll_cal_busy, // pll_cal_busy.pll_cal_busy
output wire pll_locked, // pll_locked.pll_locked
input wire pll_powerdown, // pll_powerdown.pll_powerdown
input wire pll_refclk0, // pll_refclk0.clk
output wire tx_serial_clk // tx_serial_clk.clk
);
altera_xcvr_cdr_pll_a10 #(
.enable_pll_reconfig (0),
.rcfg_jtag_enable (0),
.rcfg_separate_avmm_busy (0),
.dbg_embedded_debug_enable (0),
.dbg_capability_reg_enable (0),
.dbg_user_identifier (0),
.dbg_stat_soft_logic_enable (0),
.dbg_ctrl_soft_logic_enable (0),
.cdr_pll_silicon_rev ("20nm5"),
.cdr_pll_pma_width (8),
.cdr_pll_cgb_div (1),
.cdr_pll_is_cascaded_pll ("false"),
.cdr_pll_datarate ("5000000000 bps"),
.cdr_pll_lpd_counter (0),
.cdr_pll_lpfd_counter (2),
.cdr_pll_n_counter_scratch (1),
.cdr_pll_output_clock_frequency ("2500000000 Hz"),
.cdr_pll_reference_clock_frequency ("125000000 Hz"),
.cdr_pll_set_cdr_vco_speed (3),
.cdr_pll_set_cdr_vco_speed_fix (60),
.cdr_pll_vco_freq ("5000000000 Hz"),
.cdr_pll_atb_select_control ("atb_off"),
.cdr_pll_auto_reset_on ("auto_reset_off"),
.cdr_pll_bbpd_data_pattern_filter_select ("bbpd_data_pat_off"),
.cdr_pll_bw_sel ("medium"),
.cdr_pll_cdr_odi_select ("sel_cdr"),
.cdr_pll_cdr_phaselock_mode ("no_ignore_lock"),
.cdr_pll_cdr_powerdown_mode ("power_up"),
.cdr_pll_chgpmp_current_pd ("cp_current_pd_setting0"),
.cdr_pll_chgpmp_current_pfd ("cp_current_pfd_setting3"),
.cdr_pll_chgpmp_replicate ("false"),
.cdr_pll_chgpmp_testmode ("cp_test_disable"),
.cdr_pll_clklow_mux_select ("clklow_mux_cdr_fbclk"),
.cdr_pll_disable_up_dn ("true"),
.cdr_pll_fref_clklow_div (1),
.cdr_pll_fref_mux_select ("fref_mux_cdr_refclk"),
.cdr_pll_gpon_lck2ref_control ("gpon_lck2ref_off"),
.cdr_pll_initial_settings ("true"),
.cdr_pll_lck2ref_delay_control ("lck2ref_delay_2"),
.cdr_pll_lf_resistor_pd ("lf_pd_setting0"),
.cdr_pll_lf_resistor_pfd ("lf_pfd_setting2"),
.cdr_pll_lf_ripple_cap ("lf_no_ripple"),
.cdr_pll_loop_filter_bias_select ("lpflt_bias_7"),
.cdr_pll_ltd_ltr_micro_controller_select ("ltd_ltr_pcs"),
.cdr_pll_m_counter (20),
.cdr_pll_n_counter (1),
.cdr_pll_optimal ("false"),
.cdr_pll_pd_fastlock_mode ("false"),
.cdr_pll_pd_l_counter (0),
.cdr_pll_pfd_l_counter (2),
.cdr_pll_primary_use ("cmu"),
.cdr_pll_prot_mode ("unused"),
.cdr_pll_set_cdr_v2i_enable ("true"),
.cdr_pll_set_cdr_vco_reset ("false"),
.cdr_pll_set_cdr_vco_speed_pciegen3 ("cdr_vco_max_speedbin_pciegen3"),
.cdr_pll_pm_speed_grade ("i2"),
.cdr_pll_sup_mode ("user_mode"),
.cdr_pll_tx_pll_prot_mode ("txpll_enable"),
.cdr_pll_txpll_hclk_driver_enable ("false"),
.cdr_pll_vco_overrange_voltage ("vco_overrange_off"),
.cdr_pll_vco_underrange_voltage ("vco_underange_off"),
.cdr_pll_fb_select ("direct_fb"),
.cdr_pll_uc_ro_cal ("uc_ro_cal_on"),
.cdr_pll_iqclk_mux_sel ("power_down"),
.cdr_pll_pcie_gen ("non_pcie"),
.cdr_pll_set_cdr_input_freq_range (0),
.cdr_pll_chgpmp_current_dn_trim ("cp_current_trimming_dn_setting0"),
.cdr_pll_chgpmp_up_pd_trim_double ("normal_up_trim_current"),
.cdr_pll_chgpmp_current_up_pd ("cp_current_pd_up_setting0"),
.cdr_pll_chgpmp_current_up_trim ("cp_current_trimming_up_setting0"),
.cdr_pll_chgpmp_dn_pd_trim_double ("normal_dn_trim_current"),
.cdr_pll_cal_vco_count_length ("sel_8b_count"),
.cdr_pll_chgpmp_current_dn_pd ("cp_current_pd_dn_setting0"),
.enable_analog_resets (0),
.calibration_en ("enable"),
.pma_cdr_refclk_select_mux_silicon_rev ("20nm5"),
.pma_cdr_refclk_select_mux_refclk_select ("ref_iqclk0"),
.pma_cdr_refclk_select_mux_powerdown_mode ("powerup"),
.pma_cdr_refclk_select_mux_inclk0_logical_to_physical_mapping ("ref_iqclk0"),
.pma_cdr_refclk_select_mux_inclk1_logical_to_physical_mapping ("power_down"),
.pma_cdr_refclk_select_mux_inclk2_logical_to_physical_mapping ("power_down"),
.pma_cdr_refclk_select_mux_inclk3_logical_to_physical_mapping ("power_down"),
.pma_cdr_refclk_select_mux_inclk4_logical_to_physical_mapping ("power_down")
) xcvr_cdr_pll_a10_0 (
.pll_powerdown (pll_powerdown), // pll_powerdown.pll_powerdown
.pll_refclk0 (pll_refclk0), // pll_refclk0.clk
.tx_serial_clk (tx_serial_clk), // tx_serial_clk.clk
.pll_locked (pll_locked), // pll_locked.pll_locked
.pll_cal_busy (pll_cal_busy), // pll_cal_busy.pll_cal_busy
.pll_refclk1 (1'b0), // (terminated)
.pll_refclk2 (1'b0), // (terminated)
.pll_refclk3 (1'b0), // (terminated)
.pll_refclk4 (1'b0), // (terminated)
.reconfig_clk0 (1'b0), // (terminated)
.reconfig_reset0 (1'b0), // (terminated)
.reconfig_write0 (1'b0), // (terminated)
.reconfig_read0 (1'b0), // (terminated)
.reconfig_address0 (10'b0000000000), // (terminated)
.reconfig_writedata0 (32'b00000000000000000000000000000000), // (terminated)
.reconfig_readdata0 (), // (terminated)
.reconfig_waitrequest0 (), // (terminated)
.avmm_busy0 (), // (terminated)
.hip_cal_done () // (terminated)
);
endmodule
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_cmu_pll/wr_arria10_e3p1_cmu_pll/synth/wr_arria10_e3p1_cmu_pll_cfg.v 0 → 100644
View file @ 1983dde2
config wr_arria10_e3p1_cmu_pll_cfg;
design wr_arria10_e3p1_cmu_pll;
instance wr_arria10_e3p1_cmu_pll.xcvr_cdr_pll_a10_0 use wr_arria10_e3p1_cmu_pll_altera_xcvr_cdr_pll_a10_181.altera_xcvr_cdr_pll_a10;
endconfig
platform/altera/wr_arria10_e3p1_phy/wr_arria10_e3p1_phy/wr_arria10_e3p1_phy/synth/wr_arria10_e3p1_phy_cfg.v
View file @ 1983dde2
config wr_arria10_e3p1_phy_cfg;
design wr_arria10_e3p1_phy;
instance wr_arria10_e3p1_phy.xcvr_native_a10_0 use wr_arria10_e3p1_phy_altera_xcvr_native_a10_181.wr_arria10_e3p1_phy_altera_xcvr_native_a10_181_t6fhkiq;
instance wr_arria10_e3p1_phy.xcvr_native_a10_0 use wr_arria10_e3p1_phy_altera_xcvr_native_a10_181.wr_arria10_e3p1_phy_altera_xcvr_native_a10_181_6s7vsbi;
endconfig
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