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White Rabbit core collection
Commit 22e54748 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wr_core: cleanup, match signals names with wrpc hdl spec

parent ff2c2fab
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Showing with 164 additions and 165 deletions
modules/wrc_core/wr_core.vhd
View file @ 22e54748
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modules/wrc_core/wrcore_pkg.vhd
View file @ 22e54748
...@@ -350,8 +350,8 @@ constant c_wrc_periph3_sdb : t_sdb_device := ( ...@@ -350,8 +350,8 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
phy_rst_o : out std_logic; phy_rst_o : out std_logic;
phy_loopen_o : out std_logic; phy_loopen_o : out std_logic;
led_red_o : out std_logic; led_act_o : out std_logic;
led_green_o : out std_logic; led_link_o : out std_logic;
scl_o : out std_logic; scl_o : out std_logic;
scl_i : in std_logic; scl_i : in std_logic;
sda_o : out std_logic; sda_o : out std_logic;
...@@ -391,7 +391,7 @@ constant c_wrc_periph3_sdb : t_sdb_device := ( ...@@ -391,7 +391,7 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
tm_clk_aux_lock_en_i : in std_logic; tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_locked_o : out std_logic; tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic; tm_time_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0); tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0); tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_led_o : out std_logic; pps_led_o : out std_logic;
......
modules/wrc_core/xwr_core.vhd
View file @ 22e54748
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top/spec_1_1/wr_core_demo/spec_top.ucf
View file @ 22e54748
...@@ -629,7 +629,6 @@ TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HI ...@@ -629,7 +629,6 @@ TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HI
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
iles
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>; NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%; TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; # PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 22e54748
...@@ -619,9 +619,10 @@ begin ...@@ -619,9 +619,10 @@ begin
U_WR_CORE : xwr_core U_WR_CORE : xwr_core
generic map ( generic map (
g_simulation => 0, g_simulation => 0,
g_with_external_clock_input => true,
--
g_phys_uart => true, g_phys_uart => true,
g_virtual_uart => true, g_virtual_uart => true,
g_with_external_clock_input => true,
g_aux_clks => 1, g_aux_clks => 1,
g_ep_rxbuf_size => 1024, g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram", g_dpram_initf => "wrc.ram",
...@@ -655,8 +656,8 @@ begin ...@@ -655,8 +656,8 @@ begin
phy_rst_o => phy_rst, phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen, phy_loopen_o => phy_loopen,
led_red_o => LED_RED, led_act_o => LED_RED,
led_green_o => LED_GREEN, led_link_o => LED_GREEN,
scl_o => wrc_scl_o, scl_o => wrc_scl_o,
scl_i => wrc_scl_i, scl_i => wrc_scl_i,
sda_o => wrc_sda_o, sda_o => wrc_sda_o,
...@@ -691,7 +692,7 @@ begin ...@@ -691,7 +692,7 @@ begin
tm_clk_aux_lock_en_i => '0', tm_clk_aux_lock_en_i => '0',
tm_clk_aux_locked_o => open, tm_clk_aux_locked_o => open,
tm_time_valid_o => open, tm_time_valid_o => open,
tm_utc_o => open, tm_tai_o => open,
tm_cycles_o => open, tm_cycles_o => open,
pps_p_o => pps, pps_p_o => pps,
pps_led_o => pps_led, pps_led_o => pps_led,
......
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