wishbonized: adding link_ok output signal to the wrpc

3435d975 · Grzegorz Daniluk · 97652bb9 · 3435d975 · 3435d975
Commit 3435d975 authored Feb 16, 2012 by Grzegorz Daniluk
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Showing with 17 additions and 8 deletions

wr_core.vhd modules/wrc_core/wr_core.vhd +6 -3

xwr_core.vhd modules/wrc_core/xwr_core.vhd +11 -5

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--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk
 -- Company    : Elproma
 -- Created    : 2011-02-02
-- Last update: 2012-02-08
+-- Last update: 2012-02-17
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -196,7 +196,9 @@ entity wr_core is
    pps_p_o              : out std_logic;

    dio_o       : out std_logic_vector(3 downto 0);
-    rst_aux_n_o : out std_logic
+    rst_aux_n_o : out std_logic;
+
+    link_ok_o   : out std_logic
    );
 end wr_core;

@@ -502,7 +504,8 @@ begin
      txtsu_valid_o    => ep_txtsu_valid,
      txtsu_ack_i      => ep_txtsu_ack,
      wb_i             => ep_wb_in,
-      wb_o             => ep_wb_out);
+      wb_o             => ep_wb_out,
+      led_link_o       => link_ok_o);

  ep_txtsu_ack <= txtsu_ack_i or mnic_txtsu_ack;
  -----------------------------------------------------------------------------

--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -6,7 +6,7 @@
 -- Author     : Grzegorz Daniluk
 -- Company    : Elproma
 -- Created    : 2011-02-02
-- Last update: 2012-02-09
+-- Last update: 2012-02-17
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -158,7 +158,9 @@ entity xwr_core is
    pps_p_o              : out std_logic;

    dio_o       : out std_logic_vector(3 downto 0);
-    rst_aux_n_o : out std_logic
+    rst_aux_n_o : out std_logic;
+
+    link_ok_o   : out std_logic
    );
 end xwr_core;

@@ -169,7 +171,7 @@ architecture struct of xwr_core is
      g_simulation          : integer                        := 0;
      g_phys_uart           : boolean                        := true;
      g_virtual_uart        : boolean                        := false;
-      g_rx_buffer_size  : integer                        := 12;
+      g_rx_buffer_size      : integer                        := 12;
      g_dpram_initf         : string                         := "";
      g_dpram_size          : integer                        := 16384;  --in 32-bit words
      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
@@ -260,7 +262,9 @@ architecture struct of xwr_core is
      pps_p_o              : out std_logic;

      dio_o       : out std_logic_vector(3 downto 0);
-      rst_aux_n_o : out std_logic
+      rst_aux_n_o : out std_logic;
+
+      link_ok_o   : out std_logic
    );
  end component;

@@ -361,7 +365,9 @@ begin
      pps_p_o              => pps_p_o,

      dio_o       => dio_o,
-      rst_aux_n_o => rst_aux_n_o
+      rst_aux_n_o => rst_aux_n_o,
+
+      link_ok_o   => link_ok_o
    );

    timestamps_o.port_id(5) <= '0';