Merge branch 'ML-testbench-fix' into proposed_master

3ea2d74d · Grzegorz Daniluk · e512968a · 49239109 · 3ea2d74d · 3ea2d74d
Commit 3ea2d74d authored Nov 24, 2017 by Grzegorz Daniluk
4 changed files
--- a/bin/wrpc/wrc_phy8_sim.bram
+++ b/bin/wrpc/wrc_phy8_sim.bram
--- a/bin/wrpc/wrc_phy8_sim.mif
+++ b/bin/wrpc/wrc_phy8_sim.mif
--- a/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
+++ b/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
@@ -40,7 +40,8 @@ module main;
   // This time we have two SPECs talking to each other in the same testbench
   spec_top
     #(
-       .g_simulation (1)
+       .g_simulation (1),
+       .g_dpram_initf("../../../bin/wrpc/wrc_phy8_sim.bram")
    ) SPEC_A (
           .clk_125m_pllref_p_i (clk_ref),
           .clk_125m_pllref_n_i (~clk_ref),
@@ -64,7 +65,8 @@ module main;

   spec_top
     #(
-       .g_simulation (1)
+       .g_simulation (1),
+       .g_dpram_initf("../../../bin/wrpc/wrc_phy8_sim.bram")
    ) SPEC_B (
           .clk_125m_pllref_p_i (clk_ref),
           .clk_125m_pllref_n_i (~clk_ref),

--- a/top/spec_1_1/wr_streamers_demo/spec_top.vhd
+++ b/top/spec_1_1/wr_streamers_demo/spec_top.vhd
@@ -42,6 +42,14 @@ use work.wishbone_pkg.all;

 entity spec_top is
  generic (
+    -- setting g_dpram_initf to file path will result in syntesis/simulation using the
+    -- content of this file to run LM32 microprocessor
+    -- setting g_dpram_init to empty string (i.e."") will result in synthesis/simulation
+    -- with empty RAM for the LM32 (it will not work until code is loaded)
+    -- NOTE: the path is correct when used from the synthesis folder (this is where
+    --       ISE calls the function to find the file, the path is not correct for where
+    --       this file is stored, i.e. in the top/ folder)
+    g_dpram_initf : string  := "../../../bin/wrpc/wrc_phy8.bram";
    -- Simulation mode enable parameter. Set by default (synthesis) to 0, and
    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
@@ -514,7 +522,7 @@ begin
      g_ep_rxbuf_size             => 1024,
      g_tx_runt_padding           => true,
      g_pcs_16bit                 => false,
-      g_dpram_initf               => "../../../bin/wrpc/wrc_phy8_sim.bram",
+      g_dpram_initf               => g_dpram_initf,
 --       g_aux_sdb                   => c_etherbone_sdb, --ML
      g_dpram_size                => 131072/4,
      g_interface_mode            => PIPELINED,
@@ -707,7 +715,10 @@ begin

      -- minimum timeout: sends packets asap to minimize latency (but it's not
      -- good for large amounts of data due to encapsulation overhead)
-      g_tx_timeout => 1)
+      g_tx_timeout => 1,
+      
+      -- when simulating, the startup countdown is shorter
+      g_simulation => g_simulation)
    port map (
      clk_sys_i => clk_sys,
      rst_n_i   => rst_n,