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White Rabbit core collection
Commit 443c0581 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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minic: work in progress, use fifos

parent 3c2a6c72
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modules/wr_mini_nic/mini_nic.wb
View file @ 443c0581
......@@ -6,22 +6,16 @@ peripheral {
prefix = "minic";
hdl_entity = "minic_wb_slave";
reg {
reg {
name = "miNIC Control Register";
prefix = "MCR";
field {
name = "TX DMA start";
prefix = "TX_START";
description = "write 1: starts the DMA transmission of TX descriptors placed in the DMA buffer, write 0: no effect";
type = MONOSTABLE;
};
field {
name = "TX DMA idle";
prefix = "TX_IDLE";
description = "1: TX DMA engine is idle.\n0: TX DMA engine is busy, don't touch the buffer";
type = BIT;
align = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -36,14 +30,14 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA ready";
prefix = "RX_READY";
description = "1: RX buffer contains at least one packet";
type = BIT;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
field {
name = "RX DMA ready";
prefix = "RX_READY";
description = "1: RX buffer contains at least one packet";
type = BIT;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
......@@ -55,100 +49,151 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA enable";
prefix = "RX_EN";
description = "1: RX buffer is allocated and initialized by the host, the miNIC can receive packets\n0: RX buffer not ready, reception is disabled";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RX DMA enable";
prefix = "RX_EN";
description = "1: RX buffer is allocated and initialized by the host, the miNIC can receive packets\n0: RX buffer not ready, reception is disabled";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "TX TS ready";
prefix = "TX_TS_READY";
description = "1: the TX transfer is complete and a timestamp is available";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX TS ready";
prefix = "TX_TS_READY";
description = "1: the TX transfer is complete and a timestamp is available";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX Accepted Packet Classes";
prefix = "RX_CLASS";
size = 8;
align = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX DMA Address";
description = "Address of the start of TX buffer:\
read: base address of the last transmitted TX descriptor\
write: base address of the first descriptor to transmit";
prefix = "TX_ADDR";
field {
name = "TX DMA buffer address";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "RX Accepted Packet Classes";
prefix = "RX_CLASS";
size = 8;
align = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
reg {
name = "RX DMA Address";
description = "Address of the start of RX buffer:\
read: address of the last received RX descriptor\
write: base address of the RX buffer";
prefix = "RX_ADDR";
field {
name = "RX DMA buffer address";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "Regs map version";
prefix = "VER";
size = 4;
align = 24;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TX FIFO Register";
prefix = "TX_FIFO";
reg {
name = "RX buffer size register";
description = "Size of RX buffer in 32-bit words";
prefix = "RX_SIZE";
field {
name = "RX available words";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "Data to send";
prefix = "DAT";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
reg {
name = "RX buffer available words register";
description = "Number of available 32-bit words in the RX buffer\
read: available words in RX buffer\
write: increment available words in RX buffer";
prefix = "RX_AVAIL";
field {
name = "RX available words";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "Data type";
description = "00: normal data\
01: OOB data\
10: First word of a new frame";
prefix = "TYPE";
size = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "FIFO_EMPTY";
prefix = "EMPTY";
size = 1;
align = 30;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FIFO_FULL";
prefix = "FULL";
size = 1;
align = 31;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX FIFO Register";
prefix = "RX_FIFO";
field {
name = "Data to send";
prefix = "DAT";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Data type";
description = "00: normal data\
01: OOB data\
10: First word of a new frame";
prefix = "TYPE";
size = 2;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FIFO_EMPTY";
prefix = "EMPTY";
size = 1;
align = 30;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FIFO_FULL";
prefix = "FULL";
size = 1;
align = 31;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "reserved 1";
prefix = "RESV_1";
};
reg {
name = "reserved 2";
prefix = "RESV_2";
};
reg {
name = "TX timestamp register 0";
......
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ 443c0581
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Thu Aug 6 16:03:26 2015
-- Created : Tue Oct 11 10:43:48 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -46,8 +46,6 @@ end minic_wb_slave;
architecture syn of minic_wb_slave is
signal minic_mcr_tx_start_dly0 : std_logic ;
signal minic_mcr_tx_start_int : std_logic ;
signal minic_mcr_rx_en_int : std_logic ;
signal minic_mcr_rx_class_int : std_logic_vector(7 downto 0);
signal minic_mprot_lo_int : std_logic_vector(15 downto 0);
......@@ -89,13 +87,10 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
minic_mcr_tx_start_int <= '0';
minic_mcr_rx_en_int <= '0';
minic_mcr_rx_class_int <= "00000000";
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
regs_o.tx_fifo_dat_load_o <= '0';
regs_o.tx_fifo_type_load_o <= '0';
tx_ts_read_ack_o <= '0';
minic_mprot_lo_int <= "0000000000000000";
minic_mprot_hi_int <= "0000000000000000";
......@@ -108,32 +103,25 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
minic_mcr_tx_start_int <= '0';
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
regs_o.tx_fifo_dat_load_o <= '0';
regs_o.tx_fifo_type_load_o <= '0';
tx_ts_read_ack_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
regs_o.tx_fifo_dat_load_o <= '0';
regs_o.tx_fifo_type_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
minic_mcr_tx_start_int <= wrdata_reg(0);
minic_mcr_rx_en_int <= wrdata_reg(10);
minic_mcr_rx_class_int <= wrdata_reg(23 downto 16);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= regs_i.mcr_tx_idle_i;
rddata_reg(2) <= regs_i.mcr_tx_error_i;
rddata_reg(8) <= regs_i.mcr_rx_ready_i;
......@@ -141,6 +129,8 @@ begin
rddata_reg(10) <= minic_mcr_rx_en_int;
rddata_reg(11) <= regs_i.mcr_tx_ts_ready_i;
rddata_reg(23 downto 16) <= minic_mcr_rx_class_int;
rddata_reg(27 downto 24) <= regs_i.mcr_ver_i;
rddata_reg(0) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -150,51 +140,83 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
regs_o.tx_addr_load_o <= '1';
regs_o.tx_fifo_dat_load_o <= '1';
regs_o.tx_fifo_type_load_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.tx_addr_i;
rddata_reg(15 downto 0) <= regs_i.tx_fifo_dat_i;
rddata_reg(17 downto 16) <= regs_i.tx_fifo_type_i;
rddata_reg(30) <= regs_i.tx_fifo_empty_i;
rddata_reg(31) <= regs_i.tx_fifo_full_i;
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
regs_o.rx_addr_load_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.rx_addr_i;
rddata_reg(15 downto 0) <= regs_i.rx_fifo_dat_i;
rddata_reg(17 downto 16) <= regs_i.rx_fifo_type_i;
rddata_reg(30) <= regs_i.rx_fifo_empty_i;
rddata_reg(31) <= regs_i.rx_fifo_full_i;
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
regs_o.rx_size_load_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.rx_size_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -207,9 +229,31 @@ begin
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
regs_o.rx_avail_load_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.rx_avail_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -428,19 +472,6 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- TX DMA start
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
minic_mcr_tx_start_dly0 <= '0';
regs_o.mcr_tx_start_o <= '0';
elsif rising_edge(clk_sys_i) then
minic_mcr_tx_start_dly0 <= minic_mcr_tx_start_int;
regs_o.mcr_tx_start_o <= minic_mcr_tx_start_int and (not minic_mcr_tx_start_dly0);
end if;
end process;
-- TX DMA idle
-- TX DMA error
-- RX DMA ready
......@@ -450,14 +481,17 @@ begin
-- TX TS ready
-- RX Accepted Packet Classes
regs_o.mcr_rx_class_o <= minic_mcr_rx_class_int;
-- TX DMA buffer address
regs_o.tx_addr_o <= wrdata_reg(23 downto 0);
-- RX DMA buffer address
regs_o.rx_addr_o <= wrdata_reg(23 downto 0);
-- RX available words
regs_o.rx_size_o <= wrdata_reg(23 downto 0);
-- RX available words
regs_o.rx_avail_o <= wrdata_reg(23 downto 0);
-- Regs map version
-- Data to send
regs_o.tx_fifo_dat_o <= wrdata_reg(15 downto 0);
-- Data type
regs_o.tx_fifo_type_o <= wrdata_reg(17 downto 16);
-- FIFO_EMPTY
-- FIFO_FULL
-- Data to send
-- Data type
-- FIFO_EMPTY
-- FIFO_FULL
-- Timestamp valid
-- Port ID
-- Frame ID
......
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ 443c0581
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Thu Aug 6 16:03:26 2015
-- Created : Tue Oct 11 10:43:48 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -26,10 +26,15 @@ package minic_wbgen2_pkg is
mcr_rx_ready_i : std_logic;
mcr_rx_full_i : std_logic;
mcr_tx_ts_ready_i : std_logic;
tx_addr_i : std_logic_vector(23 downto 0);
rx_addr_i : std_logic_vector(23 downto 0);
rx_size_i : std_logic_vector(23 downto 0);
rx_avail_i : std_logic_vector(23 downto 0);
mcr_ver_i : std_logic_vector(3 downto 0);
tx_fifo_dat_i : std_logic_vector(15 downto 0);
tx_fifo_type_i : std_logic_vector(1 downto 0);
tx_fifo_empty_i : std_logic;
tx_fifo_full_i : std_logic;
rx_fifo_dat_i : std_logic_vector(15 downto 0);
rx_fifo_type_i : std_logic_vector(1 downto 0);
rx_fifo_empty_i : std_logic;
rx_fifo_full_i : std_logic;
tsr0_valid_i : std_logic;
tsr0_pid_i : std_logic_vector(4 downto 0);
tsr0_fid_i : std_logic_vector(15 downto 0);
......@@ -44,10 +49,15 @@ package minic_wbgen2_pkg is
mcr_rx_ready_i => '0',
mcr_rx_full_i => '0',
mcr_tx_ts_ready_i => '0',
tx_addr_i => (others => '0'),
rx_addr_i => (others => '0'),
rx_size_i => (others => '0'),
rx_avail_i => (others => '0'),
mcr_ver_i => (others => '0'),
tx_fifo_dat_i => (others => '0'),
tx_fifo_type_i => (others => '0'),
tx_fifo_empty_i => '0',
tx_fifo_full_i => '0',
rx_fifo_dat_i => (others => '0'),
rx_fifo_type_i => (others => '0'),
rx_fifo_empty_i => '0',
rx_fifo_full_i => '0',
tsr0_valid_i => '0',
tsr0_pid_i => (others => '0'),
tsr0_fid_i => (others => '0'),
......@@ -59,33 +69,23 @@ package minic_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_minic_out_registers is record
mcr_tx_start_o : std_logic;
mcr_rx_en_o : std_logic;
mcr_rx_class_o : std_logic_vector(7 downto 0);
tx_addr_o : std_logic_vector(23 downto 0);
tx_addr_load_o : std_logic;
rx_addr_o : std_logic_vector(23 downto 0);
rx_addr_load_o : std_logic;
rx_size_o : std_logic_vector(23 downto 0);
rx_size_load_o : std_logic;
rx_avail_o : std_logic_vector(23 downto 0);
rx_avail_load_o : std_logic;
tx_fifo_dat_o : std_logic_vector(15 downto 0);
tx_fifo_dat_load_o : std_logic;
tx_fifo_type_o : std_logic_vector(1 downto 0);
tx_fifo_type_load_o : std_logic;
mprot_lo_o : std_logic_vector(15 downto 0);
mprot_hi_o : std_logic_vector(15 downto 0);
end record;
constant c_minic_out_registers_init_value: t_minic_out_registers := (
mcr_tx_start_o => '0',
mcr_rx_en_o => '0',
mcr_rx_class_o => (others => '0'),
tx_addr_o => (others => '0'),
tx_addr_load_o => '0',
rx_addr_o => (others => '0'),
rx_addr_load_o => '0',
rx_size_o => (others => '0'),
rx_size_load_o => '0',
rx_avail_o => (others => '0'),
rx_avail_load_o => '0',
tx_fifo_dat_o => (others => '0'),
tx_fifo_dat_load_o => '0',
tx_fifo_type_o => (others => '0'),
tx_fifo_type_load_o => '0',
mprot_lo_o => (others => '0'),
mprot_hi_o => (others => '0')
);
......@@ -123,10 +123,15 @@ tmp.mcr_tx_error_i := f_x_to_zero(left.mcr_tx_error_i) or f_x_to_zero(right.mcr_
tmp.mcr_rx_ready_i := f_x_to_zero(left.mcr_rx_ready_i) or f_x_to_zero(right.mcr_rx_ready_i);
tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
tmp.mcr_tx_ts_ready_i := f_x_to_zero(left.mcr_tx_ts_ready_i) or f_x_to_zero(right.mcr_tx_ts_ready_i);
tmp.tx_addr_i := f_x_to_zero(left.tx_addr_i) or f_x_to_zero(right.tx_addr_i);
tmp.rx_addr_i := f_x_to_zero(left.rx_addr_i) or f_x_to_zero(right.rx_addr_i);
tmp.rx_size_i := f_x_to_zero(left.rx_size_i) or f_x_to_zero(right.rx_size_i);
tmp.rx_avail_i := f_x_to_zero(left.rx_avail_i) or f_x_to_zero(right.rx_avail_i);
tmp.mcr_ver_i := f_x_to_zero(left.mcr_ver_i) or f_x_to_zero(right.mcr_ver_i);
tmp.tx_fifo_dat_i := f_x_to_zero(left.tx_fifo_dat_i) or f_x_to_zero(right.tx_fifo_dat_i);
tmp.tx_fifo_type_i := f_x_to_zero(left.tx_fifo_type_i) or f_x_to_zero(right.tx_fifo_type_i);
tmp.tx_fifo_empty_i := f_x_to_zero(left.tx_fifo_empty_i) or f_x_to_zero(right.tx_fifo_empty_i);
tmp.tx_fifo_full_i := f_x_to_zero(left.tx_fifo_full_i) or f_x_to_zero(right.tx_fifo_full_i);
tmp.rx_fifo_dat_i := f_x_to_zero(left.rx_fifo_dat_i) or f_x_to_zero(right.rx_fifo_dat_i);
tmp.rx_fifo_type_i := f_x_to_zero(left.rx_fifo_type_i) or f_x_to_zero(right.rx_fifo_type_i);
tmp.rx_fifo_empty_i := f_x_to_zero(left.rx_fifo_empty_i) or f_x_to_zero(right.rx_fifo_empty_i);
tmp.rx_fifo_full_i := f_x_to_zero(left.rx_fifo_full_i) or f_x_to_zero(right.rx_fifo_full_i);
tmp.tsr0_valid_i := f_x_to_zero(left.tsr0_valid_i) or f_x_to_zero(right.tsr0_valid_i);
tmp.tsr0_pid_i := f_x_to_zero(left.tsr0_pid_i) or f_x_to_zero(right.tsr0_pid_i);
tmp.tsr0_fid_i := f_x_to_zero(left.tsr0_fid_i) or f_x_to_zero(right.tsr0_fid_i);
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ 443c0581
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