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Commit 4713a98a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_endpoint: hardware interface for online t24p transition phase calibration

parent d663c192
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Showing with 141 additions and 41 deletions
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 4713a98a
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2012-06-27
-- Last update: 2013-03-15
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -110,15 +110,15 @@ package endpoint_private_pkg is
-- Endpoint's internal fabric used to connect the submodules with each other.
-- Easier to handle than pipelined Wishbone.
type t_ep_internal_fabric is record
sof : std_logic;
eof : std_logic;
error : std_logic;
dvalid : std_logic;
bytesel : std_logic;
has_rx_timestamp : std_logic;
sof : std_logic;
eof : std_logic;
error : std_logic;
dvalid : std_logic;
bytesel : std_logic;
has_rx_timestamp : std_logic;
rx_timestamp_valid : std_logic;
data : std_logic_vector(15 downto 0);
addr : std_logic_vector(1 downto 0);
data : std_logic_vector(15 downto 0);
addr : std_logic_vector(1 downto 0);
end record;
component ep_1000basex_pcs
......@@ -252,16 +252,17 @@ package endpoint_private_pkg is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_stall_o : out std_logic;
tx_clk_i : in std_logic;
rx_clk_i : in std_logic;
ep_rmon_ram_addr_i : in std_logic_vector(4 downto 0);
ep_rmon_ram_data_o : out std_logic_vector(31 downto 0);
ep_rmon_ram_rd_i : in std_logic;
......@@ -392,32 +393,32 @@ package body endpoint_private_pkg is
fab.data <= din(15 downto 0);
if(din_valid = '1') then
if(early_eof) then
fab.dvalid <= not (not din(17) and din(16));
fab.sof <= not din(17) and din(16) and din(15);
fab.eof <= din(17);
fab.error <= not din(17) and din(16) and din(13);
fab.has_rx_timestamp <= '0';
fab.dvalid <= not (not din(17) and din(16));
fab.sof <= not din(17) and din(16) and din(15);
fab.eof <= din(17);
fab.error <= not din(17) and din(16) and din(13);
fab.has_rx_timestamp <= '0';
fab.rx_timestamp_valid <= '0';
fab.bytesel <= din(17) and din(16);
fab.bytesel <= din(17) and din(16);
else
fab.dvalid <= not din(16);
fab.sof <= din(16) and din(15);
fab.eof <= din(16) and din(14);
fab.error <= din(16) and din(13);
fab.has_rx_timestamp <= din(16) and din(12);
fab.dvalid <= not din(16);
fab.sof <= din(16) and din(15);
fab.eof <= din(16) and din(14);
fab.error <= din(16) and din(13);
fab.has_rx_timestamp <= din(16) and din(12);
fab.rx_timestamp_valid <= din(16) and din(11);
fab.bytesel <= (not din(16)) and din(17);
fab.bytesel <= (not din(16)) and din(17);
end if;
else
fab.bytesel <= 'X';
fab.dvalid <= '0';
fab.sof <= '0';
fab.eof <= '0';
fab.error <= '0';
fab.has_rx_timestamp <= '0';
fab.bytesel <= 'X';
fab.dvalid <= '0';
fab.sof <= '0';
fab.eof <= '0';
fab.error <= '0';
fab.has_rx_timestamp <= '0';
fab.rx_timestamp_valid <= '0';
fab.data <= (others => 'X');
fab.data <= (others => 'X');
end if;
end f_unpack_fifo_contents;
......
modules/wr_endpoint/ep_registers_pkg.vhd
View file @ 4713a98a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Thu Feb 14 10:46:19 2013
-- Created : Fri Mar 15 17:03:12 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -26,6 +26,7 @@ package ep_wbgen2_pkg is
ecr_feat_ptp_i : std_logic;
ecr_feat_dpi_i : std_logic;
tscr_cs_done_i : std_logic;
tscr_rx_cal_result_i : std_logic;
tcar_pcp_map_i : std_logic_vector(23 downto 0);
fcr_rxpause_i : std_logic;
fcr_txpause_i : std_logic;
......@@ -47,6 +48,7 @@ package ep_wbgen2_pkg is
ecr_feat_ptp_i => '0',
ecr_feat_dpi_i => '0',
tscr_cs_done_i => '0',
tscr_rx_cal_result_i => '0',
tcar_pcp_map_i => (others => '0'),
fcr_rxpause_i => '0',
fcr_txpause_i => '0',
......@@ -72,6 +74,7 @@ package ep_wbgen2_pkg is
tscr_en_txts_o : std_logic;
tscr_en_rxts_o : std_logic;
tscr_cs_start_o : std_logic;
tscr_rx_cal_start_o : std_logic;
rfcr_a_runt_o : std_logic;
rfcr_a_giant_o : std_logic;
rfcr_a_hp_o : std_logic;
......@@ -130,6 +133,7 @@ package ep_wbgen2_pkg is
tscr_en_txts_o => '0',
tscr_en_rxts_o => '0',
tscr_cs_start_o => '0',
tscr_rx_cal_start_o => '0',
rfcr_a_runt_o => '0',
rfcr_a_giant_o => '0',
rfcr_a_hp_o => '0',
......@@ -213,6 +217,7 @@ tmp.ecr_feat_dmtd_i := f_x_to_zero(left.ecr_feat_dmtd_i) or f_x_to_zero(right.ec
tmp.ecr_feat_ptp_i := f_x_to_zero(left.ecr_feat_ptp_i) or f_x_to_zero(right.ecr_feat_ptp_i);
tmp.ecr_feat_dpi_i := f_x_to_zero(left.ecr_feat_dpi_i) or f_x_to_zero(right.ecr_feat_dpi_i);
tmp.tscr_cs_done_i := f_x_to_zero(left.tscr_cs_done_i) or f_x_to_zero(right.tscr_cs_done_i);
tmp.tscr_rx_cal_result_i := f_x_to_zero(left.tscr_rx_cal_result_i) or f_x_to_zero(right.tscr_rx_cal_result_i);
tmp.tcar_pcp_map_i := f_x_to_zero(left.tcar_pcp_map_i) or f_x_to_zero(right.tcar_pcp_map_i);
tmp.fcr_rxpause_i := f_x_to_zero(left.fcr_rxpause_i) or f_x_to_zero(right.fcr_rxpause_i);
tmp.fcr_txpause_i := f_x_to_zero(left.fcr_txpause_i) or f_x_to_zero(right.fcr_txpause_i);
......
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @ 4713a98a
......@@ -7,7 +7,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2012-03-16
-- Last update: 2013-03-15
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -89,7 +89,7 @@ entity ep_timestamping_unit is
-------------------------------------------------------------------------------
-- TX Timestamp output (clk_ref_i clock domain)
-------------------------------------------------------------------------------
-- TX timestamp output (to TXTSU/Framer)
txts_timestamp_o : out std_logic_vector(31 downto 0);
......@@ -160,6 +160,10 @@ architecture syn of ep_timestamping_unit is
signal txts_valid : std_logic;
signal valid_rx, valid_tx : std_logic;
signal cal_count : unsigned(5 downto 0);
signal rx_trigger_mask, rx_trigger_a, rx_cal_pulse_a : std_logic;
begin -- syn
......@@ -182,6 +186,45 @@ begin -- syn
sync_done_o => regs_o.tscr_cs_done_i
);
p_rx_timestamper_calibration : process(clk_rx_i)
begin
if rising_edge(clk_rx_i) then
if rst_n_rx_i = '0' then
cal_count <= (others => '0');
rx_cal_pulse_a <= '0';
rx_trigger_mask <= '1';
elsif(regs_i.tscr_rx_cal_start_o = '1') then
cal_count <= to_unsigned(1, 6);
rx_trigger_mask <= '0';
elsif(cal_count /= 0) then
cal_count <= cal_count + 1;
if(rx_ts_done = '1') then
if(cntr_rx_f /= cntr_rx_r(g_timestamp_bits_f-1 downto 0)) then
regs_o.tscr_rx_cal_result_i <= '1';
else
regs_o.tscr_rx_cal_result_i <= '0';
end if;
end if;
else
rx_trigger_mask <= '1';
end if;
if(cal_count (5 downto 4) = x"01") then
rx_cal_pulse_a <= '1';
else
rx_cal_pulse_a <= '0';
end if;
end if;
end process;
rx_trigger_a <= (rx_timestamp_trigger_p_a_i and rx_trigger_mask) or rx_cal_pulse_a;
-- Sync chains for timestamp strobes: 4 combinations - (TX-RX) -> (rising/falling)
sync_ffs_tx_r : gc_sync_ffs
generic map (
......@@ -194,13 +237,15 @@ begin -- syn
npulse_o => open,
ppulse_o => take_tx_synced_p);
sync_ffs_rx_r : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
data_i => rx_timestamp_trigger_p_a_i,
data_i => rx_trigger_a,
synced_o => open,
npulse_o => open,
ppulse_o => take_rx_synced_p);
......@@ -223,7 +268,7 @@ begin -- syn
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
data_i => rx_timestamp_trigger_p_a_i,
data_i => rx_trigger_a,
synced_o => open,
npulse_o => open,
ppulse_o => take_rx_synced_p_fedge);
......
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ 4713a98a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Thu Feb 14 10:46:19 2013
-- Created : Fri Mar 15 17:03:12 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -32,6 +32,7 @@ entity ep_wishbone_controller is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
tx_clk_i : in std_logic;
rx_clk_i : in std_logic;
-- Ports for RAM: Event counters memory
ep_rmon_ram_addr_i : in std_logic_vector(4 downto 0);
-- Read data output
......@@ -63,6 +64,11 @@ signal ep_tscr_cs_start_sync1 : std_logic ;
signal ep_tscr_cs_start_sync2 : std_logic ;
signal ep_tscr_cs_done_sync0 : std_logic ;
signal ep_tscr_cs_done_sync1 : std_logic ;
signal ep_tscr_rx_cal_start_int : std_logic ;
signal ep_tscr_rx_cal_start_int_delay : std_logic ;
signal ep_tscr_rx_cal_start_sync0 : std_logic ;
signal ep_tscr_rx_cal_start_sync1 : std_logic ;
signal ep_tscr_rx_cal_start_sync2 : std_logic ;
signal ep_rfcr_a_runt_int : std_logic ;
signal ep_rfcr_a_giant_int : std_logic ;
signal ep_rfcr_a_hp_int : std_logic ;
......@@ -117,6 +123,8 @@ begin
ep_tscr_en_rxts_int <= '0';
ep_tscr_cs_start_int <= '0';
ep_tscr_cs_start_int_delay <= '0';
ep_tscr_rx_cal_start_int <= '0';
ep_tscr_rx_cal_start_int_delay <= '0';
ep_rfcr_a_runt_int <= '0';
ep_rfcr_a_giant_int <= '0';
ep_rfcr_a_hp_int <= '0';
......@@ -176,6 +184,8 @@ begin
else
ep_tscr_cs_start_int <= ep_tscr_cs_start_int_delay;
ep_tscr_cs_start_int_delay <= '0';
ep_tscr_rx_cal_start_int <= ep_tscr_rx_cal_start_int_delay;
ep_tscr_rx_cal_start_int_delay <= '0';
regs_o.vcr1_vid_wr_o <= '0';
regs_o.vcr1_value_wr_o <= '0';
regs_o.pfcr0_mm_addr_wr_o <= '0';
......@@ -241,13 +251,15 @@ begin
ep_tscr_en_rxts_int <= wrdata_reg(1);
ep_tscr_cs_start_int <= wrdata_reg(2);
ep_tscr_cs_start_int_delay <= wrdata_reg(2);
ep_tscr_rx_cal_start_int <= wrdata_reg(4);
ep_tscr_rx_cal_start_int_delay <= wrdata_reg(4);
end if;
rddata_reg(0) <= ep_tscr_en_txts_int;
rddata_reg(1) <= ep_tscr_en_rxts_int;
rddata_reg(2) <= '0';
rddata_reg(3) <= ep_tscr_cs_done_sync1;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(4) <= '0';
rddata_reg(5) <= regs_i.tscr_rx_cal_result_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
......@@ -750,6 +762,24 @@ begin
end process;
-- Start calibration of RX timestamper
process (rx_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.tscr_rx_cal_start_o <= '0';
ep_tscr_rx_cal_start_sync0 <= '0';
ep_tscr_rx_cal_start_sync1 <= '0';
ep_tscr_rx_cal_start_sync2 <= '0';
elsif rising_edge(rx_clk_i) then
ep_tscr_rx_cal_start_sync0 <= ep_tscr_rx_cal_start_int;
ep_tscr_rx_cal_start_sync1 <= ep_tscr_rx_cal_start_sync0;
ep_tscr_rx_cal_start_sync2 <= ep_tscr_rx_cal_start_sync1;
regs_o.tscr_rx_cal_start_o <= ep_tscr_rx_cal_start_sync2 and (not ep_tscr_rx_cal_start_sync1);
end if;
end process;
-- RX timestamper calibration result flag
-- RX accept runts
regs_o.rfcr_a_runt_o <= ep_rfcr_a_runt_int;
-- RX accept giants
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ 4713a98a
......@@ -179,6 +179,24 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "tx_clk_i";
};
field {
name = "Start calibration of RX timestamper";
prefix = "RX_CAL_START";
description = "write 1: start calibration.\
write 0: no effect";
type = MONOSTABLE;
clock = "rx_clk_i";
};
field {
name = "RX timestamper calibration result flag";
prefix = "RX_CAL_RESULT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 4713a98a
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2012-06-27
-- Last update: 2013-03-15
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -821,6 +821,7 @@ begin
wb_stall_o => open,
tx_clk_i => clk_ref_i,
rx_clk_i => phy_rx_clk_i,
ep_rmon_ram_wr_i => ep_rmon_ram_wr,
ep_rmon_ram_rd_i => ep_rmon_ram_rd,
......
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