timing/pulse_[gen|stamper].vhd: follow new WRPC port timing port names

d663c192 · Tomasz Wlostowski · d8583c2c · d663c192 · d663c192
Commit d663c192 authored Mar 15, 2013 by Tomasz Wlostowski
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Showing with 17 additions and 17 deletions

pulse_gen.vhd modules/timing/pulse_gen.vhd +8 -8

pulse_stamper.vhd modules/timing/pulse_stamper.vhd +9 -9

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--- a/modules/timing/pulse_gen.vhd
+++ b/modules/timing/pulse_gen.vhd
@@ -53,7 +53,7 @@ entity pulse_gen is
    -- produce pulses and keep trig_ready_o line permamaently active)
    tm_time_valid_i : in std_logic;
    -- number of seconds
-    tm_utc_i        : in std_logic_vector(39 downto 0);
+    tm_tai_i        : in std_logic_vector(39 downto 0);
    -- number of clk_ref_i cycles
    tm_cycles_i     : in std_logic_vector(27 downto 0);

@@ -67,9 +67,9 @@ entity pulse_gen is

    -- time at which the pulse will be produced + a single-cycle strobe to
    -- latch it in
-    trig_utc_i      : in std_logic_vector(39 downto 0);
+    trig_tai_i      : in std_logic_vector(39 downto 0);
    trig_cycles_i   : in std_logic_vector(27 downto 0);
-    trig_valid_p1_i : in std_logic
+    trig_valid_i : in std_logic
    );
 end pulse_gen;

@@ -95,8 +95,8 @@ begin  -- architecture rtl
     if rst_n_i='0' then
      trig_utc <= (others=>'0');
      trig_cycles <= (others=>'0');
-     elsif trig_valid_p1_i='1' then
-      trig_utc <= trig_utc_i;
+     elsif trig_valid_i='1' then
+      trig_utc <= trig_tai_i;
      trig_cycles <= trig_cycles_i;
     end if; 
    end if;
@@ -111,7 +111,7 @@ begin  -- architecture rtl
   if rst_n_i='0' or rst_from_sync='1' then
     trig_valid_sys_d1 <= '0';
   elsif clk_sys_i'event and clk_sys_i='1' then
-     if trig_valid_p1_i='1' then
+     if trig_valid_i='1' then
       trig_valid_sys_d1 <= '1';
     end if;
   end if;
@@ -165,7 +165,7 @@ begin  -- architecture rtl
   if rst_n_i='0' then
     trig_ready_o <= '1';
   elsif clk_sys_i'event and clk_sys_i='1' then
-     if trig_valid_p1_i='1' then
+     if trig_valid_i='1' then
       trig_ready_o <= '0';
     elsif rst_from_sync_d1='1' and rst_from_sync='0' then
     -- falling edge of reset_from_sync
@@ -188,7 +188,7 @@ begin  -- architecture rtl
   elsif clk_ref_i'event and clk_ref_i='1' then
    if tm_time_valid_i ='0' then
      pulse_o <= '0';
-    elsif tm_utc_i=trig_utc_ref and tm_cycles_i=trig_cycles_ref then
+    elsif tm_tai_i=trig_utc_ref and tm_cycles_i=trig_cycles_ref then
      pulse_o <= '1';
    else
      pulse_o <= '0';

--- a/modules/timing/pulse_stamper.vhd
+++ b/modules/timing/pulse_stamper.vhd
@@ -49,7 +49,7 @@ entity pulse_stamper is
    -- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't timestamp)
    tm_time_valid_i : in std_logic;
    -- number of seconds
-    tm_utc_i        : in std_logic_vector(39 downto 0);
+    tm_tai_i        : in std_logic_vector(39 downto 0);
    -- number of clk_ref_i cycles
    tm_cycles_i     : in std_logic_vector(27 downto 0);

@@ -57,10 +57,10 @@ entity pulse_stamper is
    ---------------------------------------------------------------------------
    -- Time tag output (clk_sys_i domain)
    ---------------------------------------------------------------------------
-    tag_utc_o      : out std_logic_vector(39 downto 0);
+    tag_tai_o      : out std_logic_vector(39 downto 0);
    tag_cycles_o   : out std_logic_vector(27 downto 0);
    -- single-cycle pulse: strobe tag on tag_utc_o and tag_cycles_o
-    tag_valid_p1_o : out std_logic
+    tag_valid_o : out std_logic
    );

  
@@ -101,7 +101,7 @@ begin  -- architecture rtl
 begin
  if clk_ref_i'event and clk_ref_i='1' then
    if pulse_ref_p1='1' and tm_time_valid_i='1' then
-      tag_utc_ref <= tm_utc_i;
+      tag_utc_ref <= tm_tai_i;
      tag_cycles_ref <= tm_cycles_i;
    end if;
  end if;
@@ -145,15 +145,15 @@ begin  -- architecture rtl
 begin
  if clk_sys_i'event and clk_sys_i='1' then
    if rst_n_i='0' then
-     tag_utc_o <= (others=>'0');
+     tag_tai_o <= (others=>'0');
     tag_cycles_o <= (others=>'0');
-     tag_valid_p1_o <= '0';
+     tag_valid_o <= '0';
    elsif pulse_sys_p1='1' then
-     tag_utc_o <= tag_utc_ref;
+     tag_tai_o <= tag_utc_ref;
     tag_cycles_o <= tag_cycles_ref;
-     tag_valid_p1_o <= '1';
+     tag_valid_o <= '1';
    else
-     tag_valid_p1_o <='0';
+     tag_valid_o <='0';
    end if;
  end if;
 end process sys_tags;