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White Rabbit core collection
Commit d663c192 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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timing/pulse_[gen|stamper].vhd: follow new WRPC port timing port names

parent d8583c2c
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Showing with 17 additions and 17 deletions
modules/timing/pulse_gen.vhd
View file @ d663c192
...@@ -53,7 +53,7 @@ entity pulse_gen is ...@@ -53,7 +53,7 @@ entity pulse_gen is
-- produce pulses and keep trig_ready_o line permamaently active) -- produce pulses and keep trig_ready_o line permamaently active)
tm_time_valid_i : in std_logic; tm_time_valid_i : in std_logic;
-- number of seconds -- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0); tm_tai_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles -- number of clk_ref_i cycles
tm_cycles_i : in std_logic_vector(27 downto 0); tm_cycles_i : in std_logic_vector(27 downto 0);
...@@ -67,9 +67,9 @@ entity pulse_gen is ...@@ -67,9 +67,9 @@ entity pulse_gen is
-- time at which the pulse will be produced + a single-cycle strobe to -- time at which the pulse will be produced + a single-cycle strobe to
-- latch it in -- latch it in
trig_utc_i : in std_logic_vector(39 downto 0); trig_tai_i : in std_logic_vector(39 downto 0);
trig_cycles_i : in std_logic_vector(27 downto 0); trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic trig_valid_i : in std_logic
); );
end pulse_gen; end pulse_gen;
...@@ -95,8 +95,8 @@ begin -- architecture rtl ...@@ -95,8 +95,8 @@ begin -- architecture rtl
if rst_n_i='0' then if rst_n_i='0' then
trig_utc <= (others=>'0'); trig_utc <= (others=>'0');
trig_cycles <= (others=>'0'); trig_cycles <= (others=>'0');
elsif trig_valid_p1_i='1' then elsif trig_valid_i='1' then
trig_utc <= trig_utc_i; trig_utc <= trig_tai_i;
trig_cycles <= trig_cycles_i; trig_cycles <= trig_cycles_i;
end if; end if;
end if; end if;
...@@ -111,7 +111,7 @@ begin -- architecture rtl ...@@ -111,7 +111,7 @@ begin -- architecture rtl
if rst_n_i='0' or rst_from_sync='1' then if rst_n_i='0' or rst_from_sync='1' then
trig_valid_sys_d1 <= '0'; trig_valid_sys_d1 <= '0';
elsif clk_sys_i'event and clk_sys_i='1' then elsif clk_sys_i'event and clk_sys_i='1' then
if trig_valid_p1_i='1' then if trig_valid_i='1' then
trig_valid_sys_d1 <= '1'; trig_valid_sys_d1 <= '1';
end if; end if;
end if; end if;
...@@ -165,7 +165,7 @@ begin -- architecture rtl ...@@ -165,7 +165,7 @@ begin -- architecture rtl
if rst_n_i='0' then if rst_n_i='0' then
trig_ready_o <= '1'; trig_ready_o <= '1';
elsif clk_sys_i'event and clk_sys_i='1' then elsif clk_sys_i'event and clk_sys_i='1' then
if trig_valid_p1_i='1' then if trig_valid_i='1' then
trig_ready_o <= '0'; trig_ready_o <= '0';
elsif rst_from_sync_d1='1' and rst_from_sync='0' then elsif rst_from_sync_d1='1' and rst_from_sync='0' then
-- falling edge of reset_from_sync -- falling edge of reset_from_sync
...@@ -188,7 +188,7 @@ begin -- architecture rtl ...@@ -188,7 +188,7 @@ begin -- architecture rtl
elsif clk_ref_i'event and clk_ref_i='1' then elsif clk_ref_i'event and clk_ref_i='1' then
if tm_time_valid_i ='0' then if tm_time_valid_i ='0' then
pulse_o <= '0'; pulse_o <= '0';
elsif tm_utc_i=trig_utc_ref and tm_cycles_i=trig_cycles_ref then elsif tm_tai_i=trig_utc_ref and tm_cycles_i=trig_cycles_ref then
pulse_o <= '1'; pulse_o <= '1';
else else
pulse_o <= '0'; pulse_o <= '0';
......
modules/timing/pulse_stamper.vhd
View file @ d663c192
...@@ -49,7 +49,7 @@ entity pulse_stamper is ...@@ -49,7 +49,7 @@ entity pulse_stamper is
-- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't timestamp) -- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't timestamp)
tm_time_valid_i : in std_logic; tm_time_valid_i : in std_logic;
-- number of seconds -- number of seconds
tm_utc_i : in std_logic_vector(39 downto 0); tm_tai_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles -- number of clk_ref_i cycles
tm_cycles_i : in std_logic_vector(27 downto 0); tm_cycles_i : in std_logic_vector(27 downto 0);
...@@ -57,10 +57,10 @@ entity pulse_stamper is ...@@ -57,10 +57,10 @@ entity pulse_stamper is
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain) -- Time tag output (clk_sys_i domain)
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
tag_utc_o : out std_logic_vector(39 downto 0); tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0); tag_cycles_o : out std_logic_vector(27 downto 0);
-- single-cycle pulse: strobe tag on tag_utc_o and tag_cycles_o -- single-cycle pulse: strobe tag on tag_utc_o and tag_cycles_o
tag_valid_p1_o : out std_logic tag_valid_o : out std_logic
); );
...@@ -101,7 +101,7 @@ begin -- architecture rtl ...@@ -101,7 +101,7 @@ begin -- architecture rtl
begin begin
if clk_ref_i'event and clk_ref_i='1' then if clk_ref_i'event and clk_ref_i='1' then
if pulse_ref_p1='1' and tm_time_valid_i='1' then if pulse_ref_p1='1' and tm_time_valid_i='1' then
tag_utc_ref <= tm_utc_i; tag_utc_ref <= tm_tai_i;
tag_cycles_ref <= tm_cycles_i; tag_cycles_ref <= tm_cycles_i;
end if; end if;
end if; end if;
...@@ -145,15 +145,15 @@ begin -- architecture rtl ...@@ -145,15 +145,15 @@ begin -- architecture rtl
begin begin
if clk_sys_i'event and clk_sys_i='1' then if clk_sys_i'event and clk_sys_i='1' then
if rst_n_i='0' then if rst_n_i='0' then
tag_utc_o <= (others=>'0'); tag_tai_o <= (others=>'0');
tag_cycles_o <= (others=>'0'); tag_cycles_o <= (others=>'0');
tag_valid_p1_o <= '0'; tag_valid_o <= '0';
elsif pulse_sys_p1='1' then elsif pulse_sys_p1='1' then
tag_utc_o <= tag_utc_ref; tag_tai_o <= tag_utc_ref;
tag_cycles_o <= tag_cycles_ref; tag_cycles_o <= tag_cycles_ref;
tag_valid_p1_o <= '1'; tag_valid_o <= '1';
else else
tag_valid_p1_o <='0'; tag_valid_o <='0';
end if; end if;
end if; end if;
end process sys_tags; end process sys_tags;
......
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