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White Rabbit core collection
Commit 49178a90 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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[streamers/review] moved component declarations and common types to 

private package, or fabric_pkg in case of fabric sink/source
parent b51202e9
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Showing with 155 additions and 181 deletions
modules/fabric/wr_fabric_pkg.vhd
View file @ 49178a90
......@@ -125,6 +125,38 @@ package wr_fabric_pkg is
wb_o : out t_wishbone_slave_out);
end component;
component xwb_fabric_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
component xwb_fabric_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic);
end component;
end wr_fabric_pkg;
package body wr_fabric_pkg is
......
modules/wr_streamers/streamers_priv_pkg.vhd
View file @ 49178a90
......@@ -36,7 +36,10 @@
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use work.wishbone_pkg.all; -- needed for t_wishbone_slave_in, etc
use work.streamers_pkg.all;
use work.wr_transmission_wbgen2_pkg.all;
package streamers_priv_pkg is
......@@ -76,6 +79,122 @@ package streamers_priv_pkg is
latency_acc_o : out std_logic_vector(g_acc_width-1 downto 0);
latency_max_o : out std_logic_vector(27 downto 0);
latency_min_o : out std_logic_vector(27 downto 0));
end component;
end component;
component wr_transmission_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_wr_transmission_in_registers;
regs_o : out t_wr_transmission_out_registers
);
end component;
-- component from wr-core/modules/timing
component pulse_stamper
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pulse_a_i : in std_logic;
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
tag_valid_o : out std_logic);
end component;
type t_pipe is record
dvalid : std_logic;
dreq : std_logic;
sof : std_logic;
eof : std_logic;
error : std_logic;
data : std_logic_vector(15 downto 0);
addr : std_logic_vector(1 downto 0);
bytesel : std_logic;
end record;
component escape_detector
generic (
g_data_width : integer;
g_escape_code : std_logic_vector);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_detect_enable_i : in std_logic;
d_valid_i : in std_logic;
d_req_o : out std_logic;
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_escape_o : out std_logic;
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
component dropping_buffer
generic (
g_size : integer;
g_data_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_req_o : out std_logic;
d_drop_i : in std_logic;
d_accept_i : in std_logic;
d_valid_i : in std_logic;
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
component gc_escape_inserter
generic (
g_data_width : integer;
g_escape_code : std_logic_vector);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_insert_enable_i : in std_logic;
d_escape_i : in std_logic;
d_valid_i : in std_logic;
d_req_o : out std_logic;
d_o : out std_logic_vector (g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
-- functions
function f_dbg_word_starting_at_bit(data_in, start_bit : std_logic_vector; g_data_width: integer) return std_logic_vector;
end streamers_priv_pkg;
package body streamers_priv_pkg is
function f_dbg_word_starting_at_bit(data_in, start_bit : std_logic_vector; g_data_width: integer) return std_logic_vector is
variable sb : integer := 0;
variable result : std_logic_vector(31 downto 0);
begin
sb := to_integer(unsigned(start_bit));
for i in 0 to 31 loop
if (sb + i < g_data_width) then
result(i) := data_in(sb + i);
else
result(i) := '0';
end if;
end loop;
return result;
end f_dbg_word_starting_at_bit;
end streamers_priv_pkg;
\ No newline at end of file
modules/wr_streamers/xrtx_streamers_stats.vhd
View file @ 49178a90
......@@ -50,7 +50,6 @@ use work.wrcore_pkg.all; -- needed for t_generic_word_array
use work.streamers_priv_pkg.all;
entity xrtx_streamers_stats is
generic (
-- Indicates whether this module instantiates both streamers (rx and tx) or only one
-- of them. An application that only receives or only transmits might want to use
......@@ -105,20 +104,6 @@ end xrtx_streamers_stats;
architecture rtl of xrtx_streamers_stats is
component pulse_stamper
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pulse_a_i : in std_logic;
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
tag_valid_o : out std_logic);
end component;
signal reset_time_tai : std_logic_vector(39 downto 0);
signal reset_time_cycles : std_logic_vector(27 downto 0);
......
modules/wr_streamers/xrx_streamer.vhd
View file @ 49178a90
......@@ -32,6 +32,7 @@ use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.streamers_priv_pkg.all;
entity xrx_streamer is
......@@ -138,81 +139,6 @@ end xrx_streamer;
architecture rtl of xrx_streamer is
type t_pipe is record
dvalid : std_logic;
dreq : std_logic;
sof : std_logic;
eof : std_logic;
error : std_logic;
data : std_logic_vector(15 downto 0);
addr : std_logic_vector(1 downto 0);
bytesel : std_logic;
end record;
component escape_detector
generic (
g_data_width : integer;
g_escape_code : std_logic_vector);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_detect_enable_i : in std_logic;
d_valid_i : in std_logic;
d_req_o : out std_logic;
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_escape_o : out std_logic;
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
component dropping_buffer
generic (
g_size : integer;
g_data_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_req_o : out std_logic;
d_drop_i : in std_logic;
d_accept_i : in std_logic;
d_valid_i : in std_logic;
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
component pulse_stamper
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pulse_a_i : in std_logic;
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
tag_valid_o : out std_logic);
end component;
component xwb_fabric_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
type t_rx_state is (IDLE, HEADER, FRAME_SEQ_ID, PAYLOAD, SUBFRAME_HEADER, EOF);
signal fab, fsm_in : t_pipe;
......
modules/wr_streamers/xtx_streamer.vhd
View file @ 49178a90
......@@ -31,9 +31,9 @@ use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.streamers_priv_pkg.all;
entity xtx_streamer is
generic (
-- Width of data words on tx_data_i, must be multiple of 16 bits.
g_data_width : integer := 32;
......@@ -136,62 +136,6 @@ end xtx_streamer;
architecture rtl of xtx_streamer is
type t_pipe is record
dvalid : std_logic;
dreq : std_logic;
sof : std_logic;
eof : std_logic;
error : std_logic;
data : std_logic_vector(15 downto 0);
end record;
component xwb_fabric_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic);
end component;
component gc_escape_inserter
generic (
g_data_width : integer;
g_escape_code : std_logic_vector);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
d_insert_enable_i : in std_logic;
d_escape_i : in std_logic;
d_valid_i : in std_logic;
d_req_o : out std_logic;
d_o : out std_logic_vector (g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
end component;
component pulse_stamper
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
pulse_a_i : in std_logic;
tm_time_valid_i : in std_logic;
tm_tai_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
tag_valid_o : out std_logic);
end component;
type t_tx_state is (IDLE, SOF, ETH_HEADER, FRAME_SEQ_ID, SUBFRAME_HEADER, PAYLOAD, CRC_WORD, PADDING, EOF);
constant c_min_packet_size : integer := 32;
......
modules/wr_streamers/xwr_transmission.vhd
View file @ 49178a90
......@@ -55,6 +55,7 @@ use work.streamers_pkg.all; -- needed for streamers and c_WR_TRANS_ARR_SIZE_*
use work.wr_fabric_pkg.all; -- needed for :t_wrf_source_in, etc
use work.wrcore_pkg.all; -- needed for t_generic_word_array
use work.wr_transmission_wbgen2_pkg.all;
use work.streamers_priv_pkg.all;
entity xwr_transmission is
generic (
......@@ -187,24 +188,6 @@ end xwr_transmission;
architecture rtl of xwr_transmission is
component wr_transmission_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_wr_transmission_in_registers;
regs_o : out t_wr_transmission_out_registers
);
end component;
signal to_wb : t_wr_transmission_in_registers;
signal from_wb : t_wr_transmission_out_registers;
signal dbg_word : std_logic_vector(31 downto 0);
......@@ -236,21 +219,6 @@ architecture rtl of xwr_transmission is
signal rx_cfg_filter_remote : std_logic;
signal rx_cfg_fixed_latency : std_logic_vector(27 downto 0);
function f_dbg_word_starting_at_bit(data_in, start_bit : std_logic_vector; g_data_width: integer) return std_logic_vector is
variable sb : integer := 0;
variable result : std_logic_vector(31 downto 0);
begin
sb := to_integer(unsigned(start_bit));
for i in 0 to 31 loop
if (sb + i < g_data_width) then
result(i) := data_in(sb + i);
else
result(i) := '0';
end if;
end loop;
return result;
end f_dbg_word_starting_at_bit;
begin
-------------------------------------------------------------------------------------------
......
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