[wr_streamers] updated wb-generated wr_streamer files

I removed BTrain-specific debugging from wr_streamers. in that commit I only updated *.wb file. now comes the update of wb-generated files

[wr_streamers] updated wb-generated wr_streamer files
I removed BTrain-specific debugging from wr_streamers. in that commit I only updated *.wb file. now comes the update of wb-generated files
51830a28 · Maciej Lipinski · Grzegorz Daniluk · 8e00d090 · 51830a28 · 51830a28
Commit 51830a28 authored May 08, 2017 by Maciej Lipinski Committed by Grzegorz Daniluk Jun 19, 2017
Showing with 3 additions and 25 deletions

wr_streamers_wb.vhd modules/wr_streamers/wr_streamers_wb.vhd +1 -15

wr_streamers_wbgen2_pkg.vhd modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd +1 -7

wr_streamers_wb.svh sim/wr_streamers_wb.svh +1 -3

No files found.
--- a/modules/wr_streamers/wr_streamers_wb.vhd
+++ b/modules/wr_streamers/wr_streamers_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wr_streamers_wb.vhd
 -- Author         : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created        : Fri Apr 21 18:02:12 2017
+-- Created        : Fri May  5 15:07:47 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
@@ -479,18 +479,6 @@ begin
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11001" => 
-            if (wb_we_i = '1') then
-            end if;
-            rddata_reg(31 downto 0) <= regs_i.dbg_rx_bvalue_i;
-            ack_sreg(0) <= '1';
-            ack_in_progress <= '1';
-          when "11010" => 
-            if (wb_we_i = '1') then
-            end if;
-            rddata_reg(31 downto 0) <= regs_i.dbg_tx_bvalue_i;
-            ack_sreg(0) <= '1';
-            ack_in_progress <= '1';
-          when "11011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.dummy_dummy_i;
@@ -598,8 +586,6 @@ begin
 -- Debug Start byte
  regs_o.dbg_ctrl_start_byte_o <= wr_streamers_dbg_ctrl_start_byte_int;
 -- Debug content
-- Debug content
-- Debug content
 -- DUMMY value to read
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);

--- a/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
+++ b/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wr_streamers_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created        : Fri Apr 21 18:02:12 2017
+-- Created        : Fri May  5 15:07:47 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
@@ -33,8 +33,6 @@ package wr_streamers_wbgen2_pkg is
    rx_stat7_rx_latency_acc_cnt_i            : std_logic_vector(31 downto 0);
    rx_stat8_rx_lost_block_cnt_i             : std_logic_vector(31 downto 0);
    dbg_data_i                               : std_logic_vector(31 downto 0);
-    dbg_rx_bvalue_i                          : std_logic_vector(31 downto 0);
-    dbg_tx_bvalue_i                          : std_logic_vector(31 downto 0);
    dummy_dummy_i                            : std_logic_vector(31 downto 0);
    end record;
@@ -52,8 +50,6 @@ package wr_streamers_wbgen2_pkg is
    rx_stat7_rx_latency_acc_cnt_i => (others => '0'),
    rx_stat8_rx_lost_block_cnt_i => (others => '0'),
    dbg_data_i => (others => '0'),
-    dbg_rx_bvalue_i => (others => '0'),
-    dbg_tx_bvalue_i => (others => '0'),
    dummy_dummy_i => (others => '0')
    );
@@ -160,8 +156,6 @@ tmp.rx_stat6_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat6_rx_latency_acc_ms
 tmp.rx_stat7_rx_latency_acc_cnt_i := f_x_to_zero(left.rx_stat7_rx_latency_acc_cnt_i) or f_x_to_zero(right.rx_stat7_rx_latency_acc_cnt_i);
 tmp.rx_stat8_rx_lost_block_cnt_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_i);
 tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
-tmp.dbg_rx_bvalue_i := f_x_to_zero(left.dbg_rx_bvalue_i) or f_x_to_zero(right.dbg_rx_bvalue_i);
-tmp.dbg_tx_bvalue_i := f_x_to_zero(left.dbg_tx_bvalue_i) or f_x_to_zero(right.dbg_tx_bvalue_i);
 tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
 return tmp;
 end function;

--- a/sim/wr_streamers_wb.svh
+++ b/sim/wr_streamers_wb.svh
@@ -101,8 +101,6 @@
 `define WR_STREAMERS_DBG_CTRL_START_BYTE_OFFSET 8
 `define WR_STREAMERS_DBG_CTRL_START_BYTE 32'h0000ff00
 `define ADDR_WR_STREAMERS_DBG_DATA     7'h60
-`define ADDR_WR_STREAMERS_DBG_RX_BVALUE 7'h64
+`define ADDR_WR_STREAMERS_DUMMY        7'h64
-`define ADDR_WR_STREAMERS_DBG_TX_BVALUE 7'h68
-`define ADDR_WR_STREAMERS_DUMMY        7'h6c
 `define WR_STREAMERS_DUMMY_DUMMY_OFFSET 0
 `define WR_STREAMERS_DUMMY_DUMMY 32'hffffffff