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White Rabbit core collection
Commit 6a20635e authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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pps_gen: separate 1-pps output to drive DIO led

parent 44f102fa
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Showing with 20 additions and 3 deletions
modules/wr_pps_gen/wr_pps_gen.vhd
View file @ 6a20635e
...@@ -63,6 +63,7 @@ entity wr_pps_gen is ...@@ -63,6 +63,7 @@ entity wr_pps_gen is
-- Single-pulse PPS output for synchronizing endpoints to -- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o : out std_logic; pps_csync_o : out std_logic;
pps_out_o : out std_logic; pps_out_o : out std_logic;
pps_led_o : out std_logic;
pps_valid_o : out std_logic; pps_valid_o : out std_logic;
...@@ -175,7 +176,7 @@ architecture behavioral of wr_pps_gen is ...@@ -175,7 +176,7 @@ architecture behavioral of wr_pps_gen is
signal retime_counter : unsigned(4 downto 0); signal retime_counter : unsigned(4 downto 0);
signal pps_valid_int : std_logic; signal pps_valid_int : std_logic;
signal pps_out_int : std_logic; signal pps_out_int : std_logic;
component chipscope_icon component chipscope_icon
...@@ -486,15 +487,19 @@ begin -- behavioral ...@@ -486,15 +487,19 @@ begin -- behavioral
if rising_edge(clk_ref_i) then if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then if rst_synced_refclk = '0' then
pps_out_int <= '0'; pps_out_int <= '0';
pps_led_o <= '0';
width_cntr <= (others => '0'); width_cntr <= (others => '0');
else else
if(ns_overflow_adv = '1') then if(ns_overflow_adv = '1') then
pps_out_int <= ppsg_escr_pps_valid; pps_out_int <= ppsg_escr_pps_valid;
width_cntr <= unsigned(ppsg_cr_pwidth); width_cntr <= unsigned(ppsg_cr_pwidth);
elsif(ns_overflow = '1') then
pps_led_o <= ppsg_escr_pps_valid;
else else
if(width_cntr = to_unsigned(0, width_cntr'length)) then if(width_cntr = to_unsigned(0, width_cntr'length)) then
pps_out_int <= '0'; pps_out_int <= '0';
pps_led_o <= '0';
else else
width_cntr <= width_cntr -1; width_cntr <= width_cntr -1;
end if; end if;
......
modules/wr_pps_gen/xwr_pps_gen.vhd
View file @ 6a20635e
...@@ -51,6 +51,7 @@ entity xwr_pps_gen is ...@@ -51,6 +51,7 @@ entity xwr_pps_gen is
-- Single-pulse PPS output for synchronizing endpoints to -- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o : out std_logic; pps_csync_o : out std_logic;
pps_out_o : out std_logic; pps_out_o : out std_logic;
pps_led_o : out std_logic;
pps_valid_o : out std_logic; pps_valid_o : out std_logic;
...@@ -88,6 +89,7 @@ architecture behavioral of xwr_pps_gen is ...@@ -88,6 +89,7 @@ architecture behavioral of xwr_pps_gen is
pps_in_i : in std_logic; pps_in_i : in std_logic;
pps_csync_o : out std_logic; pps_csync_o : out std_logic;
pps_out_o : out std_logic; pps_out_o : out std_logic;
pps_led_o : out std_logic;
pps_valid_o : out std_logic; pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0); tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0); tm_cycles_o : out std_logic_vector(27 downto 0);
...@@ -123,6 +125,7 @@ begin -- behavioral ...@@ -123,6 +125,7 @@ begin -- behavioral
pps_in_i => pps_in_i, pps_in_i => pps_in_i,
pps_csync_o => pps_csync_o, pps_csync_o => pps_csync_o,
pps_out_o => pps_out_o, pps_out_o => pps_out_o,
pps_led_o => pps_led_o,
pps_valid_o => pps_valid_o, pps_valid_o => pps_valid_o,
tm_utc_o => tm_utc_o, tm_utc_o => tm_utc_o,
tm_cycles_o => tm_cycles_o, tm_cycles_o => tm_cycles_o,
......
modules/wrc_core/wr_core.vhd
View file @ 6a20635e
...@@ -236,6 +236,7 @@ entity wr_core is ...@@ -236,6 +236,7 @@ entity wr_core is
tm_cycles_o : out std_logic_vector(27 downto 0); tm_cycles_o : out std_logic_vector(27 downto 0);
-- 1PPS output -- 1PPS output
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_led_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0); dio_o : out std_logic_vector(3 downto 0);
...@@ -463,6 +464,7 @@ begin ...@@ -463,6 +464,7 @@ begin
pps_in_i => pps_ext_i, pps_in_i => pps_ext_i,
pps_csync_o => s_pps_csync, pps_csync_o => s_pps_csync,
pps_out_o => pps_p_o, pps_out_o => pps_p_o,
pps_led_o => pps_led_o,
pps_valid_o => pps_valid, pps_valid_o => pps_valid,
tm_utc_o => tm_utc_o, tm_utc_o => tm_utc_o,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 6a20635e
...@@ -47,6 +47,7 @@ package wrcore_pkg is ...@@ -47,6 +47,7 @@ package wrcore_pkg is
pps_in_i : in std_logic; pps_in_i : in std_logic;
pps_csync_o : out std_logic; pps_csync_o : out std_logic;
pps_out_o : out std_logic; pps_out_o : out std_logic;
pps_led_o : out std_logic;
pps_valid_o : out std_logic; pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0); tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0); tm_cycles_o : out std_logic_vector(27 downto 0);
...@@ -393,6 +394,7 @@ constant c_wrc_periph3_sdb : t_sdb_device := ( ...@@ -393,6 +394,7 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
tm_utc_o : out std_logic_vector(39 downto 0); tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0); tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_led_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0); dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic; rst_aux_n_o : out std_logic;
......
modules/wrc_core/xwr_core.vhd
View file @ 6a20635e
...@@ -179,6 +179,7 @@ entity xwr_core is ...@@ -179,6 +179,7 @@ entity xwr_core is
tm_cycles_o : out std_logic_vector(27 downto 0); tm_cycles_o : out std_logic_vector(27 downto 0);
-- 1PPS output -- 1PPS output
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_led_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0); dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic; rst_aux_n_o : out std_logic;
...@@ -309,6 +310,7 @@ architecture struct of xwr_core is ...@@ -309,6 +310,7 @@ architecture struct of xwr_core is
tm_utc_o : out std_logic_vector(39 downto 0); tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0); tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic; pps_p_o : out std_logic;
pps_led_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0); dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic; rst_aux_n_o : out std_logic;
...@@ -437,6 +439,7 @@ begin ...@@ -437,6 +439,7 @@ begin
tm_utc_o => tm_utc_o, tm_utc_o => tm_utc_o,
tm_cycles_o => tm_cycles_o, tm_cycles_o => tm_cycles_o,
pps_p_o => pps_p_o, pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
dio_o => dio_o, dio_o => dio_o,
rst_aux_n_o => rst_aux_n_o, rst_aux_n_o => rst_aux_n_o,
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 6a20635e
...@@ -325,7 +325,8 @@ architecture rtl of spec_top is ...@@ -325,7 +325,8 @@ architecture rtl of spec_top is
signal dac_hpll_data : std_logic_vector(15 downto 0); signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0); signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic; signal pps : std_logic;
signal pps_led : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0); signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic; signal phy_tx_k : std_logic;
...@@ -699,6 +700,7 @@ begin ...@@ -699,6 +700,7 @@ begin
tm_utc_o => open, tm_utc_o => open,
tm_cycles_o => open, tm_cycles_o => open,
pps_p_o => pps, pps_p_o => pps,
pps_led_o => pps_led,
dio_o => dio_out(4 downto 1), dio_o => dio_out(4 downto 1),
rst_aux_n_o => etherbone_rst_n rst_aux_n_o => etherbone_rst_n
...@@ -810,7 +812,7 @@ begin ...@@ -810,7 +812,7 @@ begin
port map ( port map (
clk_i => clk_125m_pllref, clk_i => clk_125m_pllref,
rst_n_i => local_reset_n, rst_n_i => local_reset_n,
pulse_i => '0', --pps, pulse_i => pps_led,
extended_o => dio_led_top_o); extended_o => dio_led_top_o);
......
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