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White Rabbit core collection
Commit 81bb3d0a authored by Stefan Rauch's avatar Stefan Rauch
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phy: arria2 core update

parent 7ede53fb
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platform/altera/wr_arria2_phy/arria2_phy.txt
View file @ 81bb3d0a
......@@ -3,9 +3,13 @@
-- VERSION: WM1.0
-- MODULE: alt4gxb
--alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" effective_data_rate="1250.0 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=1 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="125.0 MHz" intended_device_speed_grade="5" intended_device_variant="ANY" loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="iqtxrxclk" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="cpri" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="none" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=10 rx_common_mode="0.82v" rx_cru_bandwidth_type="low" rx_cru_inclock0_period=8000 rx_cru_m_divider=5 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=4 rx_data_rate=1250 rx_data_rate_remainder=0 rx_datapath_low_latency_mode="false" rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_flip_rx_out="false" rx_force_signal_detect="true" rx_phfiforegmode="true" rx_ppmselect=9 rx_rate_match_fifo_mode="none" rx_run_length=160 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="false" rx_use_clkout="true" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_rising_edge_triggered_pattern_align="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="none" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_bitslip_enable="true" tx_channel_width=10 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=1250 tx_data_rate_remainder=0 tx_datapath_low_latency_mode="false" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_flip_tx_in="false" tx_force_disparity_mode="false" tx_phfiforegmode="true" tx_pll_bandwidth_type="medium" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=8000 tx_pll_m_divider=5 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=4 tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_bitslipboundaryselectout rx_clkout rx_cruclk rx_datain rx_dataout rx_digitalreset rx_enapatternalign rx_freqlocked rx_patterndetect rx_pll_locked rx_seriallpbken rx_syncstatus tx_bitslipboundaryselect tx_clkout tx_datain tx_dataout tx_digitalreset
--VERSION_BEGIN 11.1SP1 cbx_alt4gxb 2011:11:23:21:11:17:SJ cbx_mgl 2011:11:23:21:12:03:SJ cbx_tgx 2011:11:23:21:11:17:SJ VERSION_END
--VERSION_BEGIN 16.0 cbx_alt4gxb 2016:05:25:18:37:14:SJ cbx_mgl 2016:05:25:19:47:45:SJ cbx_tgx 2016:05:25:18:37:14:SJ VERSION_END
--synthesis_resources = arriaii_hssi_calibration_block 1 arriaii_hssi_clock_divider 1 arriaii_hssi_cmu 1 arriaii_hssi_pll 2 arriaii_hssi_rx_pcs 1 arriaii_hssi_rx_pma 1 arriaii_hssi_tx_pcs 1 arriaii_hssi_tx_pma 1
-- ============================================================
-- CNX file retrieval info
......@@ -220,5 +224,4 @@
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriaii_hssi
-- Retrieval info: CBX_MODULE_PREFIX: ON
platform/altera/wr_arria2_phy/arria2_phy_reconf.txt
View file @ 81bb3d0a
......@@ -3,12 +3,17 @@
-- VERSION: WM1.0
-- MODULE: alt2gxb_reconfig
--alt2gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Arria II GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=1 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=17 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
--VERSION_BEGIN 11.1 cbx_alt2gxb_reconfig 2011:10:31:21:09:45:SJ cbx_alt_cal 2011:10:31:21:09:45:SJ cbx_alt_dprio 2011:10:31:21:09:45:SJ cbx_altsyncram 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_counter 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_mux 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ cbx_stratixiii 2011:10:31:21:09:45:SJ cbx_stratixv 2011:10:31:21:09:45:SJ cbx_util_mgl 2011:10:31:21:09:45:SJ VERSION_END
--VERSION_BEGIN 16.0 cbx_alt2gxb_reconfig 2016:05:25:18:37:14:SJ cbx_alt_cal 2016:05:25:18:37:14:SJ cbx_alt_dprio 2016:05:25:18:37:14:SJ cbx_altera_syncram_nd_impl 2016:05:25:18:37:14:SJ cbx_altsyncram 2016:05:25:18:37:14:SJ cbx_cycloneii 2016:05:25:18:37:14:SJ cbx_lpm_add_sub 2016:05:25:18:37:14:SJ cbx_lpm_compare 2016:05:25:18:37:14:SJ cbx_lpm_counter 2016:05:25:18:37:14:SJ cbx_lpm_decode 2016:05:25:18:37:14:SJ cbx_lpm_mux 2016:05:25:18:37:14:SJ cbx_lpm_shiftreg 2016:05:25:18:37:14:SJ cbx_mgl 2016:05:25:19:47:45:SJ cbx_nadder 2016:05:25:18:37:14:SJ cbx_stratix 2016:05:25:18:37:14:SJ cbx_stratixii 2016:05:25:18:37:14:SJ cbx_stratixiii 2016:05:25:18:37:15:SJ cbx_stratixv 2016:05:25:18:37:15:SJ cbx_util_mgl 2016:05:25:18:37:14:SJ VERSION_END
--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
--VERSION_BEGIN 11.1 cbx_alt_dprio 2011:10:31:21:09:45:SJ cbx_cycloneii 2011:10:31:21:09:45:SJ cbx_lpm_add_sub 2011:10:31:21:09:45:SJ cbx_lpm_compare 2011:10:31:21:09:45:SJ cbx_lpm_counter 2011:10:31:21:09:45:SJ cbx_lpm_decode 2011:10:31:21:09:45:SJ cbx_lpm_shiftreg 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_stratix 2011:10:31:21:09:45:SJ cbx_stratixii 2011:10:31:21:09:45:SJ VERSION_END
--VERSION_BEGIN 16.0 cbx_alt_dprio 2016:05:25:18:37:14:SJ cbx_cycloneii 2016:05:25:18:37:14:SJ cbx_lpm_add_sub 2016:05:25:18:37:14:SJ cbx_lpm_compare 2016:05:25:18:37:14:SJ cbx_lpm_counter 2016:05:25:18:37:14:SJ cbx_lpm_decode 2016:05:25:18:37:14:SJ cbx_lpm_shiftreg 2016:05:25:18:37:14:SJ cbx_mgl 2016:05:25:19:47:45:SJ cbx_nadder 2016:05:25:18:37:14:SJ cbx_stratix 2016:05:25:18:37:14:SJ cbx_stratixii 2016:05:25:18:37:14:SJ VERSION_END
--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102
-- ============================================================
-- CNX file retrieval info
......@@ -40,5 +45,3 @@
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_phy_reconf_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
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