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White Rabbit core collection
Commits
9a125269
Commit
9a125269
authored
Jan 23, 2019
by
li hongming
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Plain Diff
change g_flash_secsz_kb to g_flash_secsz_kB.
Add a new I2C interface in wrc_syscon for SFP1.
parent
0303489d
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12 changed files
with
315 additions
and
37 deletions
+315
-37
wr_board_pkg.vhd
board/common/wr_board_pkg.vhd
+1
-1
xwrc_board_common.vhd
board/common/xwrc_board_common.vhd
+18
-14
xwrc_board_cute.vhd
board/cute/xwrc_board_cute.vhd
+54
-3
wr_core.vhd
modules/wrc_core/wr_core.vhd
+12
-2
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+34
-2
wrc_syscon_pkg.vhd
modules/wrc_core/wrc_syscon_pkg.vhd
+23
-2
wrc_syscon_regs.h
modules/wrc_core/wrc_syscon_regs.h
+17
-2
wrc_syscon_wb.vhd
modules/wrc_core/wrc_syscon_wb.vhd
+65
-5
wrc_syscon_wb.wb
modules/wrc_core/wrc_syscon_wb.wb
+51
-1
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+18
-3
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+12
-2
wrc_syscon_regs.vh
sim/wrc_syscon_regs.vh
+10
-0
No files found.
board/common/wr_board_pkg.vhd
View file @
9a125269
...
...
@@ -96,7 +96,7 @@ package wr_board_pkg is
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
boolean
:
=
TRUE
;
g_board_name
:
string
:
=
"NA "
;
g_flash_secsz_k
b
:
integer
:
=
256
;
-- default for M25P128
g_flash_secsz_k
B
:
integer
:
=
256
;
-- default for M25P128
g_flash_sdbfs_baddr
:
integer
:
=
16
#
600000
#
;
-- default for M25P128
g_phys_uart
:
boolean
:
=
TRUE
;
g_virtual_uart
:
boolean
:
=
TRUE
;
...
...
board/common/xwrc_board_common.vhd
View file @
9a125269
...
...
@@ -51,7 +51,7 @@ entity xwrc_board_common is
g_simulation
:
integer
:
=
0
;
g_with_external_clock_input
:
boolean
:
=
TRUE
;
g_board_name
:
string
:
=
"NA "
;
g_flash_secsz_k
b
:
integer
:
=
256
;
-- default for M25P128
g_flash_secsz_k
B
:
integer
:
=
256
;
-- default for M25P128
g_flash_sdbfs_baddr
:
integer
:
=
16
#
600000
#
;
-- default for M25P128
g_phys_uart
:
boolean
:
=
TRUE
;
g_virtual_uart
:
boolean
:
=
TRUE
;
...
...
@@ -340,12 +340,12 @@ architecture struct of xwrc_board_common is
signal
sfp_sda_in
:
std_logic
;
signal
sfp_det_in
:
std_logic
;
-- ch1 - currently unconnected
- not supported at the moment (TODO)
--
signal sfp1_scl_out : std_logic;
--
signal sfp1_scl_in : std_logic;
--
signal sfp1_sda_out : std_logic;
--
signal sfp1_sda_in : std_logic;
--
signal sfp1_det_in : std_logic;
-- ch1 - currently unconnected
signal
sfp1_scl_out
:
std_logic
;
signal
sfp1_scl_in
:
std_logic
;
signal
sfp1_sda_out
:
std_logic
;
signal
sfp1_sda_in
:
std_logic
;
signal
sfp1_det_in
:
std_logic
;
begin
-- architecture struct
...
...
@@ -366,7 +366,7 @@ begin -- architecture struct
g_simulation
=>
g_simulation
,
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_board_name
=>
g_board_name
,
g_flash_secsz_k
b
=>
g_flash_secsz_kb
,
g_flash_secsz_k
B
=>
g_flash_secsz_kB
,
g_flash_sdbfs_baddr
=>
g_flash_sdbfs_baddr
,
g_phys_uart
=>
g_phys_uart
,
g_virtual_uart
=>
g_virtual_uart
,
...
...
@@ -435,6 +435,11 @@ begin -- architecture struct
sfp_sda_o
=>
sfp_sda_out
,
sfp_sda_i
=>
sfp_sda_in
,
sfp_det_i
=>
sfp_det_in
,
sfp1_scl_o
=>
sfp1_scl_out
,
sfp1_scl_i
=>
sfp1_scl_in
,
sfp1_sda_o
=>
sfp1_sda_out
,
sfp1_sda_i
=>
sfp1_sda_in
,
sfp1_det_i
=>
sfp1_det_in
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
spi_sclk_o
=>
spi_sclk_o
,
...
...
@@ -634,12 +639,11 @@ begin -- architecture struct
sfp_sda_in
<=
sfp_sda_i
;
sfp_det_in
<=
sfp_det_i
;
-- at the moment, only one channel si supported (TODO)
-- sfp1_scl_o <= sfp1_scl_out;
-- sfp1_scl_in<= sfp1_scl_i;
-- sfp1_sda_o <= sfp1_sda_out;
-- sfp1_sda_in<= sfp1_sda_i;
-- sfp1_det_in<= sfp1_det_i;
sfp1_scl_o
<=
sfp1_scl_out
;
sfp1_scl_in
<=
sfp1_scl_i
;
sfp1_sda_o
<=
sfp1_sda_out
;
sfp1_sda_in
<=
sfp1_sda_i
;
sfp1_det_in
<=
sfp1_det_i
;
end
generate
gen_sfp_i2c_dual
;
...
...
board/cute/xwrc_board_cute.vhd
View file @
9a125269
...
...
@@ -388,6 +388,19 @@ architecture struct of xwrc_board_cute is
signal
sfp_tx_fault_in
:
std_logic
;
signal
sfp_tx_disable_out
:
std_logic
;
signal
sfp_los_in
:
std_logic
;
signal
sfp1_txp_out
:
std_logic
;
signal
sfp1_txn_out
:
std_logic
;
signal
sfp1_rxp_in
:
std_logic
;
signal
sfp1_rxn_in
:
std_logic
;
signal
sfp1_det_in
:
std_logic
;
signal
sfp1_sda_in
:
std_logic
;
signal
sfp1_sda_out
:
std_logic
;
signal
sfp1_scl_in
:
std_logic
;
signal
sfp1_scl_out
:
std_logic
;
signal
sfp1_tx_fault_in
:
std_logic
;
signal
sfp1_tx_disable_out
:
std_logic
;
signal
sfp1_los_in
:
std_logic
;
signal
tm_time_valid
:
std_logic
;
...
...
@@ -477,7 +490,7 @@ begin -- architecture struct
-- SFP0/1 selection
-----------------------------------------------------------------------------
GEN_GTP0
:
if
g_sfp0_enable
=
1
generate
GEN_GTP0
:
if
(
g_sfp0_enable
=
1
)
and
(
g_sfp1_enable
=
0
)
generate
clk_125m_gtp_p
<=
clk_125m_gtp0_p_i
;
clk_125m_gtp_n
<=
clk_125m_gtp0_n_i
;
...
...
@@ -495,7 +508,7 @@ begin -- architecture struct
sfp_los_in
<=
sfp0_los_i
;
end
generate
;
GEN_GTP1
:
if
g_sfp1_enable
=
1
generate
GEN_GTP1
:
if
(
g_sfp0_enable
=
0
)
and
(
g_sfp1_enable
=
1
)
generate
clk_125m_gtp_p
<=
clk_125m_gtp1_p_i
;
clk_125m_gtp_n
<=
clk_125m_gtp1_n_i
;
...
...
@@ -512,6 +525,39 @@ begin -- architecture struct
sfp_tx_fault_in
<=
sfp1_tx_fault_i
;
sfp_los_in
<=
sfp1_los_i
;
end
generate
;
GEN_GTP0_and_GTP1
:
if
(
g_sfp0_enable
=
1
)
and
(
g_sfp1_enable
=
1
)
generate
clk_125m_gtp_p
<=
clk_125m_gtp0_p_i
;
clk_125m_gtp_n
<=
clk_125m_gtp0_n_i
;
sfp0_txp_o
<=
sfp_txp_out
;
sfp0_txn_o
<=
sfp_txn_out
;
sfp0_sda_o
<=
sfp_sda_out
;
sfp0_scl_o
<=
sfp_scl_out
;
sfp0_tx_disable_o
<=
sfp_tx_disable_out
;
sfp_rxp_in
<=
sfp0_rxp_i
;
sfp_rxn_in
<=
sfp0_rxn_i
;
sfp_det_in
<=
sfp0_det_i
;
sfp_sda_in
<=
sfp0_sda_i
;
sfp_scl_in
<=
sfp0_scl_i
;
sfp_tx_fault_in
<=
sfp0_tx_fault_i
;
sfp_los_in
<=
sfp0_los_i
;
sfp1_txp_o
<=
sfp1_txp_out
;
sfp1_txn_o
<=
sfp1_txn_out
;
sfp1_sda_o
<=
sfp1_sda_out
;
sfp1_scl_o
<=
sfp1_scl_out
;
sfp1_tx_disable_o
<=
sfp1_tx_disable_out
;
sfp1_rxp_in
<=
sfp1_rxp_i
;
sfp1_rxn_in
<=
sfp1_rxn_i
;
sfp1_det_in
<=
sfp1_det_i
;
sfp1_sda_in
<=
sfp1_sda_i
;
sfp1_scl_in
<=
sfp1_scl_i
;
sfp1_tx_fault_in
<=
sfp1_tx_fault_i
;
sfp1_los_in
<=
sfp1_los_i
;
end
generate
;
sfp0_rate_select_o
<=
'1'
;
sfp1_rate_select_o
<=
'1'
;
...
...
@@ -600,7 +646,7 @@ begin -- architecture struct
g_simulation
=>
g_simulation
,
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_board_name
=>
"CUTE"
,
g_flash_secsz_k
b
=>
64
,
-- sector size for M25P32
g_flash_secsz_k
B
=>
64
,
-- sector size for M25P32
g_flash_sdbfs_baddr
=>
16
#
2
e0000
#
,
-- sdbfs after multiboot bitstream
g_phys_uart
=>
TRUE
,
g_virtual_uart
=>
TRUE
,
...
...
@@ -651,6 +697,11 @@ begin -- architecture struct
sfp_sda_o
=>
sfp_sda_out
,
sfp_sda_i
=>
sfp_sda_in
,
sfp_det_i
=>
sfp_det_in
,
sfp1_scl_o
=>
sfp1_scl_out
,
sfp1_scl_i
=>
sfp1_scl_in
,
sfp1_sda_o
=>
sfp1_sda_out
,
sfp1_sda_i
=>
sfp1_sda_in
,
sfp1_det_i
=>
sfp1_det_in
,
spi_sclk_o
=>
flash_sclk_o
,
spi_ncs_o
=>
flash_ncs_o
,
spi_mosi_o
=>
flash_mosi_o
,
...
...
modules/wrc_core/wr_core.vhd
View file @
9a125269
...
...
@@ -77,7 +77,7 @@ entity wr_core is
g_with_external_clock_input
:
boolean
:
=
true
;
--
g_board_name
:
string
:
=
"NA "
;
g_flash_secsz_k
b
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_secsz_k
B
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_sdbfs_baddr
:
integer
:
=
16
#
600000
#
;
-- default for SVEC (M25P128)
g_phys_uart
:
boolean
:
=
true
;
g_virtual_uart
:
boolean
:
=
true
;
...
...
@@ -179,6 +179,11 @@ entity wr_core is
sfp_sda_o
:
out
std_logic
;
sfp_sda_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp1_scl_o
:
out
std_logic
;
sfp1_scl_i
:
in
std_logic
:
=
'1'
;
sfp1_sda_o
:
out
std_logic
;
sfp1_sda_i
:
in
std_logic
:
=
'1'
;
sfp1_det_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
spi_sclk_o
:
out
std_logic
;
...
...
@@ -877,7 +882,7 @@ begin
PERIPH
:
wrc_periph
generic
map
(
g_board_name
=>
g_board_name
,
g_flash_secsz_k
b
=>
g_flash_secsz_kb
,
g_flash_secsz_k
B
=>
g_flash_secsz_kB
,
g_flash_sdbfs_baddr
=>
g_flash_sdbfs_baddr
,
g_phys_uart
=>
g_phys_uart
,
g_virtual_uart
=>
g_virtual_uart
,
...
...
@@ -911,6 +916,11 @@ begin
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
sfp1_scl_o
=>
sfp1_scl_o
,
sfp1_scl_i
=>
sfp1_scl_i
,
sfp1_sda_o
=>
sfp1_sda_o
,
sfp1_sda_i
=>
sfp1_sda_i
,
sfp1_det_i
=>
sfp1_det_i
,
slave_i
=>
periph_slave_i
,
slave_o
=>
periph_slave_o
,
...
...
modules/wrc_core/wrc_periph.vhd
View file @
9a125269
...
...
@@ -48,7 +48,7 @@ use work.wrc_diags_wbgen2_pkg.all;
entity
wrc_periph
is
generic
(
g_board_name
:
string
:
=
"NA "
;
g_flash_secsz_k
b
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_secsz_k
B
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_sdbfs_baddr
:
integer
:
=
16
#
600000
#
;
-- default for SVEC (M25P128)
g_phys_uart
:
boolean
:
=
true
;
g_virtual_uart
:
boolean
:
=
false
;
...
...
@@ -78,6 +78,11 @@ entity wrc_periph is
sfp_sda_o
:
out
std_logic
;
sfp_sda_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
;
sfp1_scl_o
:
out
std_logic
;
sfp1_scl_i
:
in
std_logic
:
=
'1'
;
sfp1_sda_o
:
out
std_logic
;
sfp1_sda_i
:
in
std_logic
:
=
'1'
;
sfp1_det_i
:
in
std_logic
:
=
'1'
;
memsize_i
:
in
std_logic_vector
(
3
downto
0
);
btn1_i
:
in
std_logic
;
btn2_i
:
in
std_logic
;
...
...
@@ -195,7 +200,7 @@ begin
-- BOARD NAME and Flash info
-------------------------------------
sysc_regs_i
.
hwir_name_i
<=
f_board_name_conv
(
g_board_name
);
sysc_regs_i
.
hwfr_storage_sec_i
<=
std_logic_vector
(
to_unsigned
(
g_flash_secsz_k
b
,
16
));
sysc_regs_i
.
hwfr_storage_sec_i
<=
std_logic_vector
(
to_unsigned
(
g_flash_secsz_k
B
,
16
));
sysc_regs_i
.
hwfr_storage_type_i
<=
"00"
;
-- for now these parameters are only for Flash
sysc_regs_i
.
sdbfs_baddr_i
<=
std_logic_vector
(
to_unsigned
(
g_flash_sdbfs_baddr
,
32
));
...
...
@@ -292,6 +297,33 @@ begin
sysc_regs_i
.
gpsr_sfp_scl_i
<=
sfp_scl_i
;
sysc_regs_i
.
gpsr_sfp_det_i
<=
sfp_det_i
;
p_drive_sfp1i2c
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
sfp1_scl_o
<=
'1'
;
sfp1_sda_o
<=
'1'
;
else
if
(
sysc_regs_o
.
gpsr_sfp1_sda_load_o
=
'1'
and
sysc_regs_o
.
gpsr_sfp1_sda_o
=
'1'
)
then
sfp1_sda_o
<=
'1'
;
elsif
(
sysc_regs_o
.
gpcr_sfp1_sda_o
=
'1'
)
then
sfp1_sda_o
<=
'0'
;
end
if
;
if
(
sysc_regs_o
.
gpsr_sfp1_scl_load_o
=
'1'
and
sysc_regs_o
.
gpsr_sfp1_scl_o
=
'1'
)
then
sfp1_scl_o
<=
'1'
;
elsif
(
sysc_regs_o
.
gpcr_sfp1_scl_o
=
'1'
)
then
sfp1_scl_o
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
sysc_regs_i
.
gpsr_sfp1_sda_i
<=
sfp1_sda_i
;
sysc_regs_i
.
gpsr_sfp1_scl_i
<=
sfp1_scl_i
;
sysc_regs_i
.
gpsr_sfp1_det_i
<=
sfp1_det_i
;
-------------------------------------
-- SPI - Flash
...
...
modules/wrc_core/wrc_syscon_pkg.vhd
View file @
9a125269
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created :
Mon Nov 27 13:37:56 2017
-- Created :
Tue Jan 22 16:51:52 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...
...
@@ -31,6 +31,9 @@ package sysc_wbgen2_pkg is
gpsr_spi_ncs_i
:
std_logic
;
gpsr_spi_mosi_i
:
std_logic
;
gpsr_spi_miso_i
:
std_logic
;
gpsr_sfp1_det_i
:
std_logic
;
gpsr_sfp1_scl_i
:
std_logic
;
gpsr_sfp1_sda_i
:
std_logic
;
hwfr_memsize_i
:
std_logic_vector
(
3
downto
0
);
hwfr_storage_type_i
:
std_logic_vector
(
1
downto
0
);
hwfr_storage_sec_i
:
std_logic_vector
(
15
downto
0
);
...
...
@@ -59,6 +62,9 @@ package sysc_wbgen2_pkg is
gpsr_spi_ncs_i
=>
'0'
,
gpsr_spi_mosi_i
=>
'0'
,
gpsr_spi_miso_i
=>
'0'
,
gpsr_sfp1_det_i
=>
'0'
,
gpsr_sfp1_scl_i
=>
'0'
,
gpsr_sfp1_sda_i
=>
'0'
,
hwfr_memsize_i
=>
(
others
=>
'0'
),
hwfr_storage_type_i
=>
(
others
=>
'0'
),
hwfr_storage_sec_i
=>
(
others
=>
'0'
),
...
...
@@ -98,6 +104,10 @@ package sysc_wbgen2_pkg is
gpsr_spi_ncs_load_o
:
std_logic
;
gpsr_spi_mosi_o
:
std_logic
;
gpsr_spi_mosi_load_o
:
std_logic
;
gpsr_sfp1_scl_o
:
std_logic
;
gpsr_sfp1_scl_load_o
:
std_logic
;
gpsr_sfp1_sda_o
:
std_logic
;
gpsr_sfp1_sda_load_o
:
std_logic
;
gpcr_led_stat_o
:
std_logic
;
gpcr_led_link_o
:
std_logic
;
gpcr_fmc_scl_o
:
std_logic
;
...
...
@@ -107,6 +117,8 @@ package sysc_wbgen2_pkg is
gpcr_spi_sclk_o
:
std_logic
;
gpcr_spi_cs_o
:
std_logic
;
gpcr_spi_mosi_o
:
std_logic
;
gpcr_sfp1_scl_o
:
std_logic
;
gpcr_sfp1_sda_o
:
std_logic
;
tcr_enable_o
:
std_logic
;
diag_cr_adr_o
:
std_logic_vector
(
15
downto
0
);
diag_cr_adr_load_o
:
std_logic
;
...
...
@@ -157,6 +169,10 @@ package sysc_wbgen2_pkg is
gpsr_spi_ncs_load_o
=>
'0'
,
gpsr_spi_mosi_o
=>
'0'
,
gpsr_spi_mosi_load_o
=>
'0'
,
gpsr_sfp1_scl_o
=>
'0'
,
gpsr_sfp1_scl_load_o
=>
'0'
,
gpsr_sfp1_sda_o
=>
'0'
,
gpsr_sfp1_sda_load_o
=>
'0'
,
gpcr_led_stat_o
=>
'0'
,
gpcr_led_link_o
=>
'0'
,
gpcr_fmc_scl_o
=>
'0'
,
...
...
@@ -166,6 +182,8 @@ package sysc_wbgen2_pkg is
gpcr_spi_sclk_o
=>
'0'
,
gpcr_spi_cs_o
=>
'0'
,
gpcr_spi_mosi_o
=>
'0'
,
gpcr_sfp1_scl_o
=>
'0'
,
gpcr_sfp1_sda_o
=>
'0'
,
tcr_enable_o
=>
'0'
,
diag_cr_adr_o
=>
(
others
=>
'0'
),
diag_cr_adr_load_o
=>
'0'
,
...
...
@@ -212,7 +230,7 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
x
(
i
)
=
'1'
then
if
(
x
(
i
)
=
'1'
)
then
tmp
(
i
):
=
'1'
;
else
tmp
(
i
):
=
'0'
;
...
...
@@ -234,6 +252,9 @@ tmp.gpsr_spi_sclk_i := f_x_to_zero(left.gpsr_spi_sclk_i) or f_x_to_zero(right.gp
tmp
.
gpsr_spi_ncs_i
:
=
f_x_to_zero
(
left
.
gpsr_spi_ncs_i
)
or
f_x_to_zero
(
right
.
gpsr_spi_ncs_i
);
tmp
.
gpsr_spi_mosi_i
:
=
f_x_to_zero
(
left
.
gpsr_spi_mosi_i
)
or
f_x_to_zero
(
right
.
gpsr_spi_mosi_i
);
tmp
.
gpsr_spi_miso_i
:
=
f_x_to_zero
(
left
.
gpsr_spi_miso_i
)
or
f_x_to_zero
(
right
.
gpsr_spi_miso_i
);
tmp
.
gpsr_sfp1_det_i
:
=
f_x_to_zero
(
left
.
gpsr_sfp1_det_i
)
or
f_x_to_zero
(
right
.
gpsr_sfp1_det_i
);
tmp
.
gpsr_sfp1_scl_i
:
=
f_x_to_zero
(
left
.
gpsr_sfp1_scl_i
)
or
f_x_to_zero
(
right
.
gpsr_sfp1_scl_i
);
tmp
.
gpsr_sfp1_sda_i
:
=
f_x_to_zero
(
left
.
gpsr_sfp1_sda_i
)
or
f_x_to_zero
(
right
.
gpsr_sfp1_sda_i
);
tmp
.
hwfr_memsize_i
:
=
f_x_to_zero
(
left
.
hwfr_memsize_i
)
or
f_x_to_zero
(
right
.
hwfr_memsize_i
);
tmp
.
hwfr_storage_type_i
:
=
f_x_to_zero
(
left
.
hwfr_storage_type_i
)
or
f_x_to_zero
(
right
.
hwfr_storage_type_i
);
tmp
.
hwfr_storage_sec_i
:
=
f_x_to_zero
(
left
.
hwfr_storage_sec_i
)
or
f_x_to_zero
(
right
.
hwfr_storage_sec_i
);
...
...
modules/wrc_core/wrc_syscon_regs.h
View file @
9a125269
...
...
@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created :
Mon Nov 27 13:37:56 2017
* Created :
Tue Jan 22 16:51:52 2019
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...
...
@@ -90,6 +90,15 @@
/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MISO WBGEN2_GEN_MASK(13, 1)
/* definitions for field: SFP1 detect (MOD_DEF0 signal) in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_DET WBGEN2_GEN_MASK(16, 1)
/* definitions for field: SFP1 I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_SCL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: SFP1 I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_SDA WBGEN2_GEN_MASK(18, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
...
...
@@ -107,7 +116,7 @@
/* definitions for field: SFP I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SCL WBGEN2_GEN_MASK(8, 1)
/* definitions for field:
FMC
I2C bitbanged SDA in reg: GPIO Clear Register */
/* definitions for field:
SFP
I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Clear Register */
...
...
@@ -119,6 +128,12 @@
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
/* definitions for field: SFP1 I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP1_SCL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: SFP1 I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP1_SDA WBGEN2_GEN_MASK(18, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
...
...
modules/wrc_core/wrc_syscon_wb.vhd
View file @
9a125269
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created :
Mon Nov 27 13:37:56 2017
-- Created :
Tue Jan 22 16:51:52 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...
...
@@ -29,6 +29,8 @@ entity wrc_syscon_wb is
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_sysc_in_registers
;
regs_o
:
out
t_sysc_out_registers
...
...
@@ -62,6 +64,10 @@ signal sysc_gpcr_spi_cs_dly0 : std_logic ;
signal
sysc_gpcr_spi_cs_int
:
std_logic
;
signal
sysc_gpcr_spi_mosi_dly0
:
std_logic
;
signal
sysc_gpcr_spi_mosi_int
:
std_logic
;
signal
sysc_gpcr_sfp1_scl_dly0
:
std_logic
;
signal
sysc_gpcr_sfp1_scl_int
:
std_logic
;
signal
sysc_gpcr_sfp1_sda_dly0
:
std_logic
;
signal
sysc_gpcr_sfp1_sda_int
:
std_logic
;
signal
sysc_tcr_enable_int
:
std_logic
;
signal
sysc_diag_cr_rw_int
:
std_logic
;
signal
sysc_wdiag_ctrl_data_valid_int
:
std_logic
;
...
...
@@ -88,8 +94,13 @@ signal sysc_wdiag_temp_int : std_logic_vector(31 downto 0);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
4
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments
...
...
@@ -114,6 +125,8 @@ begin
regs_o
.
gpsr_spi_sclk_load_o
<=
'0'
;
regs_o
.
gpsr_spi_ncs_load_o
<=
'0'
;
regs_o
.
gpsr_spi_mosi_load_o
<=
'0'
;
regs_o
.
gpsr_sfp1_scl_load_o
<=
'0'
;
regs_o
.
gpsr_sfp1_sda_load_o
<=
'0'
;
sysc_gpcr_led_stat_int
<=
'0'
;
sysc_gpcr_led_link_int
<=
'0'
;
sysc_gpcr_fmc_scl_int
<=
'0'
;
...
...
@@ -123,6 +136,8 @@ begin
sysc_gpcr_spi_sclk_int
<=
'0'
;
sysc_gpcr_spi_cs_int
<=
'0'
;
sysc_gpcr_spi_mosi_int
<=
'0'
;
sysc_gpcr_sfp1_scl_int
<=
'0'
;
sysc_gpcr_sfp1_sda_int
<=
'0'
;
sysc_tcr_enable_int
<=
'0'
;
regs_o
.
diag_cr_adr_load_o
<=
'0'
;
sysc_diag_cr_rw_int
<=
'0'
;
...
...
@@ -165,6 +180,8 @@ begin
regs_o
.
gpsr_spi_sclk_load_o
<=
'0'
;
regs_o
.
gpsr_spi_ncs_load_o
<=
'0'
;
regs_o
.
gpsr_spi_mosi_load_o
<=
'0'
;
regs_o
.
gpsr_sfp1_scl_load_o
<=
'0'
;
regs_o
.
gpsr_sfp1_sda_load_o
<=
'0'
;
sysc_gpcr_led_stat_int
<=
'0'
;
sysc_gpcr_led_link_int
<=
'0'
;
sysc_gpcr_fmc_scl_int
<=
'0'
;
...
...
@@ -174,6 +191,8 @@ begin
sysc_gpcr_spi_sclk_int
<=
'0'
;
sysc_gpcr_spi_cs_int
<=
'0'
;
sysc_gpcr_spi_mosi_int
<=
'0'
;
sysc_gpcr_sfp1_scl_int
<=
'0'
;
sysc_gpcr_sfp1_sda_int
<=
'0'
;
regs_o
.
diag_cr_adr_load_o
<=
'0'
;
regs_o
.
diag_dat_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
...
...
@@ -186,6 +205,8 @@ begin
regs_o
.
gpsr_spi_sclk_load_o
<=
'0'
;
regs_o
.
gpsr_spi_ncs_load_o
<=
'0'
;
regs_o
.
gpsr_spi_mosi_load_o
<=
'0'
;
regs_o
.
gpsr_sfp1_scl_load_o
<=
'0'
;
regs_o
.
gpsr_sfp1_sda_load_o
<=
'0'
;
regs_o
.
diag_cr_adr_load_o
<=
'0'
;
regs_o
.
diag_dat_load_o
<=
'0'
;
end
if
;
...
...
@@ -243,6 +264,8 @@ begin
regs_o
.
gpsr_spi_sclk_load_o
<=
'1'
;
regs_o
.
gpsr_spi_ncs_load_o
<=
'1'
;
regs_o
.
gpsr_spi_mosi_load_o
<=
'1'
;
regs_o
.
gpsr_sfp1_scl_load_o
<=
'1'
;
regs_o
.
gpsr_sfp1_sda_load_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'0'
;
rddata_reg
(
1
)
<=
'0'
;
...
...
@@ -258,11 +281,11 @@ begin
rddata_reg
(
11
)
<=
regs_i
.
gpsr_spi_ncs_i
;
rddata_reg
(
12
)
<=
regs_i
.
gpsr_spi_mosi_i
;
rddata_reg
(
13
)
<=
regs_i
.
gpsr_spi_miso_i
;
rddata_reg
(
16
)
<=
regs_i
.
gpsr_sfp1_det_i
;
rddata_reg
(
17
)
<=
regs_i
.
gpsr_sfp1_scl_i
;
rddata_reg
(
18
)
<=
regs_i
.
gpsr_sfp1_sda_i
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
...
...
@@ -289,6 +312,8 @@ begin
sysc_gpcr_spi_sclk_int
<=
wrdata_reg
(
10
);
sysc_gpcr_spi_cs_int
<=
wrdata_reg
(
11
);
sysc_gpcr_spi_mosi_int
<=
wrdata_reg
(
12
);
sysc_gpcr_sfp1_scl_int
<=
wrdata_reg
(
17
);
sysc_gpcr_sfp1_sda_int
<=
wrdata_reg
(
18
);
end
if
;
rddata_reg
(
0
)
<=
'0'
;
rddata_reg
(
1
)
<=
'0'
;
...
...
@@ -299,6 +324,8 @@ begin
rddata_reg
(
10
)
<=
'0'
;
rddata_reg
(
11
)
<=
'0'
;
rddata_reg
(
12
)
<=
'0'
;
rddata_reg
(
17
)
<=
'0'
;
rddata_reg
(
18
)
<=
'0'
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
...
...
@@ -789,6 +816,11 @@ begin
-- SPI bitbanged MOSI
regs_o
.
gpsr_spi_mosi_o
<=
wrdata_reg
(
12
);
-- SPI bitbanged MISO
-- SFP1 detect (MOD_DEF0 signal)
-- SFP1 I2C bitbanged SCL
regs_o
.
gpsr_sfp1_scl_o
<=
wrdata_reg
(
17
);
-- SFP1 I2C bitbanged SDA
regs_o
.
gpsr_sfp1_sda_o
<=
wrdata_reg
(
18
);
-- Status LED
process
(
clk_sys_i
,
rst_n_i
)
begin
...
...
@@ -854,7 +886,7 @@ begin
end
process
;
--
FMC
I2C bitbanged SDA
--
SFP
I2C bitbanged SDA
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
...
...
@@ -906,6 +938,32 @@ begin
end
process
;
-- SFP1 I2C bitbanged SCL
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
sysc_gpcr_sfp1_scl_dly0
<=
'0'
;
regs_o
.
gpcr_sfp1_scl_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
sysc_gpcr_sfp1_scl_dly0
<=
sysc_gpcr_sfp1_scl_int
;
regs_o
.
gpcr_sfp1_scl_o
<=
sysc_gpcr_sfp1_scl_int
and
(
not
sysc_gpcr_sfp1_scl_dly0
);
end
if
;
end
process
;
-- SFP1 I2C bitbanged SDA
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
sysc_gpcr_sfp1_sda_dly0
<=
'0'
;
regs_o
.
gpcr_sfp1_sda_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
sysc_gpcr_sfp1_sda_dly0
<=
sysc_gpcr_sfp1_sda_int
;
regs_o
.
gpcr_sfp1_sda_o
<=
sysc_gpcr_sfp1_sda_int
and
(
not
sysc_gpcr_sfp1_sda_dly0
);
end
if
;
end
process
;
-- Memory size
-- Storage type
-- Storage sector size
...
...
@@ -970,6 +1028,8 @@ begin
regs_o
.
wdiag_temp_o
<=
sysc_wdiag_temp_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_err_o
<=
'0'
;
wb_rty_o
<=
'0'
;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
modules/wrc_core/wrc_syscon_wb.wb
View file @
9a125269
...
...
@@ -175,6 +175,40 @@ peripheral {
align = 13;
};
field {
name = "SFP1 detect (MOD_DEF0 signal)";
prefix = "sfp1_det";
description = "read : returns the state of the SFP1's MOD_DEF0 line";
type = BIT;
align = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SFP1 I2C bitbanged SCL";
prefix = "sfp1_scl";
description = "write 1: Set SFP1 SCL line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 17;
};
field {
name = "SFP1 I2C bitbanged SDA";
prefix = "sfp1_sda";
description = "write 1: Set SFP1 SDA line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
align = 18;
};
};
reg {
...
...
@@ -220,7 +254,7 @@ peripheral {
};
field {
name = "
FMC
I2C bitbanged SDA";
name = "
SFP
I2C bitbanged SDA";
prefix = "sfp_sda";
description = "write 1: Set SFP SDA line to 0.";
type = MONOSTABLE;
...
...
@@ -251,6 +285,22 @@ peripheral {
align = 12;
};
field {
name = "SFP1 I2C bitbanged SCL";
prefix = "sfp1_scl";
description = "write 1: Set SFP1 SCL line to 0.";
type = MONOSTABLE;
align = 17;
};
field {
name = "SFP1 I2C bitbanged SDA";
prefix = "sfp1_sda";
description = "write 1: Set SFP1 SDA line to 0.";
type = MONOSTABLE;
align = 18;
};
};
reg {
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
9a125269
...
...
@@ -243,7 +243,7 @@ package wrcore_pkg is
component
wrc_periph
is
generic
(
g_board_name
:
string
:
=
"NA "
;
g_flash_secsz_k
b
:
integer
:
=
64
;
g_flash_secsz_k
B
:
integer
:
=
64
;
g_flash_sdbfs_baddr
:
integer
:
=
16
#
2
e0000
#
;
g_phys_uart
:
boolean
:
=
true
;
g_virtual_uart
:
boolean
:
=
false
;
...
...
@@ -278,6 +278,11 @@ package wrcore_pkg is
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
sfp1_scl_o
:
out
std_logic
;
sfp1_scl_i
:
in
std_logic
:
=
'1'
;
sfp1_sda_o
:
out
std_logic
;
sfp1_sda_i
:
in
std_logic
:
=
'1'
;
sfp1_det_i
:
in
std_logic
:
=
'1'
;
slave_i
:
in
t_wishbone_slave_in_array
(
0
to
3
);
slave_o
:
out
t_wishbone_slave_out_array
(
0
to
3
);
uart_rxd_i
:
in
std_logic
;
...
...
@@ -362,7 +367,7 @@ package wrcore_pkg is
generic
(
g_simulation
:
integer
:
=
0
;
g_board_name
:
string
:
=
"NA "
;
g_flash_secsz_k
b
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_secsz_k
B
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_sdbfs_baddr
:
integer
:
=
16
#
600000
#
;
-- default for SVEC (M25P128)
g_phys_uart
:
boolean
:
=
true
;
g_virtual_uart
:
boolean
:
=
true
;
...
...
@@ -441,6 +446,11 @@ package wrcore_pkg is
sfp_sda_o
:
out
std_logic
;
sfp_sda_i
:
in
std_logic
:
=
'H'
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp1_scl_o
:
out
std_logic
;
sfp1_scl_i
:
in
std_logic
:
=
'1'
;
sfp1_sda_o
:
out
std_logic
;
sfp1_sda_i
:
in
std_logic
:
=
'1'
;
sfp1_det_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'H'
;
btn2_i
:
in
std_logic
:
=
'H'
;
spi_sclk_o
:
out
std_logic
;
...
...
@@ -505,7 +515,7 @@ package wrcore_pkg is
g_with_external_clock_input
:
boolean
:
=
true
;
--
g_board_name
:
string
:
=
"NA "
;
g_flash_secsz_k
b
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_secsz_k
B
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_sdbfs_baddr
:
integer
:
=
16
#
600000
#
;
-- default for SVEC (M25P128)
g_phys_uart
:
boolean
:
=
true
;
g_virtual_uart
:
boolean
:
=
true
;
...
...
@@ -611,6 +621,11 @@ package wrcore_pkg is
sfp_sda_o
:
out
std_logic
;
sfp_sda_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp1_scl_o
:
out
std_logic
;
sfp1_scl_i
:
in
std_logic
:
=
'1'
;
sfp1_sda_o
:
out
std_logic
;
sfp1_sda_i
:
in
std_logic
:
=
'1'
;
sfp1_det_i
:
in
std_logic
:
=
'1'
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
spi_sclk_o
:
out
std_logic
;
...
...
modules/wrc_core/xwr_core.vhd
View file @
9a125269
...
...
@@ -76,7 +76,7 @@ entity xwr_core is
g_with_external_clock_input
:
boolean
:
=
true
;
--
g_board_name
:
string
:
=
"NA "
;
g_flash_secsz_k
b
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_secsz_k
B
:
integer
:
=
256
;
-- default for SVEC (M25P128)
g_flash_sdbfs_baddr
:
integer
:
=
16
#
600000
#
;
-- default for SVEC (M25P128)
g_phys_uart
:
boolean
:
=
true
;
g_virtual_uart
:
boolean
:
=
true
;
...
...
@@ -182,6 +182,11 @@ entity xwr_core is
sfp_sda_o
:
out
std_logic
;
sfp_sda_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
;
sfp1_scl_o
:
out
std_logic
;
sfp1_scl_i
:
in
std_logic
:
=
'1'
;
sfp1_sda_o
:
out
std_logic
;
sfp1_sda_i
:
in
std_logic
:
=
'1'
;
sfp1_det_i
:
in
std_logic
;
btn1_i
:
in
std_logic
:
=
'1'
;
btn2_i
:
in
std_logic
:
=
'1'
;
spi_sclk_o
:
out
std_logic
;
...
...
@@ -275,7 +280,7 @@ begin
generic
map
(
g_simulation
=>
g_simulation
,
g_board_name
=>
g_board_name
,
g_flash_secsz_k
b
=>
g_flash_secsz_kb
,
g_flash_secsz_k
B
=>
g_flash_secsz_kB
,
g_flash_sdbfs_baddr
=>
g_flash_sdbfs_baddr
,
g_phys_uart
=>
g_phys_uart
,
g_virtual_uart
=>
g_virtual_uart
,
...
...
@@ -350,6 +355,11 @@ begin
sfp_sda_o
=>
sfp_sda_o
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_det_i
=>
sfp_det_i
,
sfp1_scl_o
=>
sfp1_scl_o
,
sfp1_scl_i
=>
sfp1_scl_i
,
sfp1_sda_o
=>
sfp1_sda_o
,
sfp1_sda_i
=>
sfp1_sda_i
,
sfp1_det_i
=>
sfp1_det_i
,
btn1_i
=>
btn1_i
,
btn2_i
=>
btn2_i
,
spi_sclk_o
=>
spi_sclk_o
,
...
...
sim/wrc_syscon_regs.vh
View file @
9a125269
...
...
@@ -32,6 +32,12 @@
`define SYSC_GPSR_SPI_MOSI 32'h00001000
`define SYSC_GPSR_SPI_MISO_OFFSET 13
`define SYSC_GPSR_SPI_MISO 32'h00002000
`define SYSC_GPSR_SFP1_DET_OFFSET 16
`define SYSC_GPSR_SFP1_DET 32'h00010000
`define SYSC_GPSR_SFP1_SCL_OFFSET 17
`define SYSC_GPSR_SFP1_SCL 32'h00020000
`define SYSC_GPSR_SFP1_SDA_OFFSET 18
`define SYSC_GPSR_SFP1_SDA 32'h00040000
`define ADDR_SYSC_GPCR 7'h8
`define SYSC_GPCR_LED_STAT_OFFSET 0
`define SYSC_GPCR_LED_STAT 32'h00000001
...
...
@@ -51,6 +57,10 @@
`define SYSC_GPCR_SPI_CS 32'h00000800
`define SYSC_GPCR_SPI_MOSI_OFFSET 12
`define SYSC_GPCR_SPI_MOSI 32'h00001000
`define SYSC_GPCR_SFP1_SCL_OFFSET 17
`define SYSC_GPCR_SFP1_SCL 32'h00020000
`define SYSC_GPCR_SFP1_SDA_OFFSET 18
`define SYSC_GPCR_SFP1_SDA 32'h00040000
`define ADDR_SYSC_HWFR 7'hc
`define SYSC_HWFR_MEMSIZE_OFFSET 0
`define SYSC_HWFR_MEMSIZE 32'h0000000f
...
...
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