[streamers/review] unified headers/license

9c807d70 · Maciej Lipinski · Grzegorz Daniluk · 49178a90 · 9c807d70 · 9c807d70
Commit 9c807d70 authored Apr 20, 2017 by Maciej Lipinski Committed by Grzegorz Daniluk Jun 19, 2017
12 changed files
--- a/modules/wr_streamers/dropping_buffer.vhd
+++ b/modules/wr_streamers/dropping_buffer.vhd
+-------------------------------------------------------------------------------
+-- Title      : Dropping buffer
+-- Project    : WR Stramers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : dropping_buffer.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-11-02
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- A FIFO that can be cleared fast
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use work.genram_pkg.all; -- needed for f_log2_size()
-use work.genram_pkg.all;
 entity dropping_buffer is
  generic (
    g_size       : integer;
    g_data_width : integer);

--- a/modules/wr_streamers/gc_escape_detector.vhd
+++ b/modules/wr_streamers/gc_escape_detector.vhd
+-------------------------------------------------------------------------------
+-- Title      : Escape detecotr
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : escape_detector.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-10-01
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- It detects the "escape code" (e.g.0xCAFE) and removes it from the data stream.
+-- See escape_inserter for details
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/wr_streamers/gc_escape_inserter.vhd
+++ b/modules/wr_streamers/gc_escape_inserter.vhd
 -------------------------------------------------------------------------------
 -- Title      : Escape insertion unit
-- Project    : General cores library
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
 -------------------------------------------------------------------------------
 -- File       : gc_escape_inserter.vhd
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2012-10-01
-- Last update: 2012-10-10
 -- Platform   : FPGA-generic
 -- Standard   : VHDL '93
 ------------------------------------------------------------------------------

--- a/modules/wr_streamers/rx_streamer.vhd
+++ b/modules/wr_streamers/rx_streamer.vhd
-- see xrx_streamer.vhd for port documentation
+-------------------------------------------------------------------------------
+-- Title      : Wrapper for xrx_streamer
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : rx_streamer.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-10-01
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- Wrapper for xrx_streamer that is needed/used for SystemVerilog simulation
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/wr_streamers/streamers_pkg.vhd
+++ b/modules/wr_streamers/streamers_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : Package for WR Steamers
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : streamers_pkg.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-10-01
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- Package with declaration of streamer components, types and constants.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use work.wr_fabric_pkg.all;

--- a/modules/wr_streamers/tx_streamer.vhd
+++ b/modules/wr_streamers/tx_streamer.vhd
-- see xtx_streamer.vhd for comments
+-------------------------------------------------------------------------------
+-- Title      : Wrapper for xtx_streamer
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
+-------------------------------------------------------------------------------
+-- File       : tx_streamer.vhd
+-- Author     : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-- Created    : 2012-10-01
+-------------------------------------------------------------------------------
+-- Description:
+--
+-- Wrapper for xtx_streamer that is needed/used for SystemVerilog simulation
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/wr_streamers/xrtx_streamers_stats.vhd
+++ b/modules/wr_streamers/xrtx_streamers_stats.vhd
 -------------------------------------------------------------------------------
 -- Title      : WR Streamers statistics
-- Project    : White Rabbit Streamers
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
 -------------------------------------------------------------------------------
 -- File       : xrtx_streamers_stats.vhd
 -- Author     : Maciej Lipinski
 -- Company    : CERN
 -- Created    : 2016-06-08
-- Last update: 2016-06-12
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
 -- Description:
-- 
+-- Module to collect, reset, snapshot statistics from the streamers. The
+-- statistics are made available through wishbone I/F (outside this entity)
+-- and diags_i/o (generic input/output arrays of 32-bit registers). Wishbone I/F
+-- can be read via bus (PCI, VME,...). Diags can be read via wrpc commands and 
+-- SNMP.
+--
+-- The module provides basic statistics such as:
+-- * number of sent/received streamer frames
+-- * number of lost frames/blocks
+-- * accumulated latency of streamer frames
+-- * count of the accumulated latencies
+-- * max/min latency
+-- * timestamp of the reset pulse
+--
+-- The module allows to snapshot the statistics values as to have a coherent
+-- view.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2016 CERN/BE-CO-HT
+-- Copyright (c) 2016-2017CERN/BE-CO-HT
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   
@@ -33,11 +48,7 @@
 -- from http://www.gnu.org/licenses/lgpl-2.1.html
 --
 -------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author          Description
-- 2016-06-08  1.0      mlipinsk        created
-- 2016-06-12  1.1      mlipinsk        added generic word arrays for SNMP
---------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;

--- a/modules/wr_streamers/xrx_streamer.vhd
+++ b/modules/wr_streamers/xrx_streamer.vhd
 -------------------------------------------------------------------------------
-- Title      : Simple Ethernet Data Streamer
+-- Title      : Transmission Streamer
-- Project    : White Rabbit Hands-On Course
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
 -------------------------------------------------------------------------------
 -- File       : xrx_streamer.vhd
 -- Author     : Tomasz Wlostowski
@@ -14,14 +15,23 @@
 -- the White Rabbit PTP core. This core decodes Ethernet frames encoded by
 -- xtx_streamer. More info in the documentation.
 -------------------------------------------------------------------------------
-- Copyright (c) 2013 CERN BE-CO-HT.
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
-- Licensed under LGPL 2.1.
+--
-------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it
-- Revisions  :
+-- and/or modify it under the terms of the GNU Lesser General
-- Date        Version  Author                Description
+-- Public License as published by the Free Software Foundation;
-- 2012-11-02  1.0      Tomasz Wlostowski     Created
+-- either version 2.1 of the License, or (at your option) any
-- 2016-03-31  2.0      Maciej Lipinski       made B-train backward compatible 
+-- later version.
--                                            & debugged
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 library ieee;

--- a/modules/wr_streamers/xrx_streamers_stats.vhd
+++ b/modules/wr_streamers/xrx_streamers_stats.vhd
@@ -10,7 +10,9 @@
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
 -- Description:
-- 
+-- This module provies the reception portion of statistics and
+-- allows to snapshot their values. See xrtx_streamers_stats for
+-- more detailed description.
 -------------------------------------------------------------------------------
 --
 -- Copyright (c) 2016 CERN/BE-CO-HT

--- a/modules/wr_streamers/xtx_streamer.vhd
+++ b/modules/wr_streamers/xtx_streamer.vhd
 -------------------------------------------------------------------------------
-- Title      : Simple Ethernet Data Streamer
+-- Title      : Reception streamer
-- Project    : White Rabbit Hands-On Course
+-- Project    : WR streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
 -------------------------------------------------------------------------------
 -- File       : xtx_streamer.vhd
 -- Author     : Tomasz Wlostowski
@@ -13,14 +14,23 @@
 -- stream of data words into Ethernet frames, in a format that is accepted by
 -- the White Rabbit PTP core. More info in the documentation.
 -------------------------------------------------------------------------------
-- Copyright (c) 2013 CERN BE-CO-HT.
+-- Copyright (c) 2012-2017 CERN/BE-CO-HT
-- Licensed under LGPL 2.1.
+--
-------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it
-- Revisions  :
+-- and/or modify it under the terms of the GNU Lesser General
-- Date        Version  Author                Description
+-- Public License as published by the Free Software Foundation;
-- 2012-11-02  1.0      Tomasz Wlostowski     Created
+-- either version 2.1 of the License, or (at your option) any
-- 2016-03-30  2.0      Maciej Lipinski       made B-train backward compatible 
+-- later version.
--                                            & debugged
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 library ieee;

--- a/modules/wr_streamers/xtx_streamers_stats.vhd
+++ b/modules/wr_streamers/xtx_streamers_stats.vhd
 -------------------------------------------------------------------------------
-- Title      : WR tx Streamers statistics
+-- Title      : WR tx streamers statistics
-- Project    : White Rabbit Streamers
+-- Project    : WR streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
 -------------------------------------------------------------------------------
 -- File       : xrtx_streamers_stats.vhd
 -- Author     : Maciej Lipinski
@@ -10,7 +11,9 @@
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
 -- Description:
-- 
+-- This module provies the reception portion of statistics and
+-- allows to snapshot their values. See xrtx_streamers_stats for
+-- more detailed description.
 -------------------------------------------------------------------------------
 --
 -- Copyright (c) 2017 CERN/BE-CO-HT

--- a/modules/wr_streamers/xwr_transmission.vhd
+++ b/modules/wr_streamers/xwr_transmission.vhd
 -------------------------------------------------------------------------------
-- Title      : Btrain over White Rabbit
+-- Title      : WR Streamrs
-- Project    : Btrain
+-- Project    : WR Streamers
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
 -------------------------------------------------------------------------------
 -- File       : xwr_transmission.vhd
 -- Author     : Maciej Lipinski
 -- Company    : CERN
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
+-- Created    : 2016-05-30
 -------------------------------------------------------------------------------
 -- Description:
 --
@@ -39,10 +41,6 @@
 -- Public License along with this source; if not, download it
 -- from http://www.gnu.org/licenses/lgpl-2.1.html
 --
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author          Description
-- 2016-05-30  1.0      mlipinsk        created
 ---------------------------------------------------------------------------------
 library IEEE;