Add prototype timing cores to the project Manifest so that hdlmake can see them.

ab7d69d1 · Wesley W. Terpstra · c1e6807b · ab7d69d1 · ab7d69d1 · ab7d69d1
Commit ab7d69d1 authored Sep 11, 2012 by Wesley W. Terpstra
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Manifest.py Manifest.py +2 -0

xwr_eca_pkg.vhd modules/wr_eca/xwr_eca_pkg.vhd +1 -0

Manifest.py modules/wr_tlu/Manifest.py +1 -0

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--- a/Manifest.py
+++ b/Manifest.py
@@ -9,6 +9,8 @@ modules =  {"local" :
 												"modules/wr_endpoint",
 												"modules/wr_pps_gen",
 												"modules/wr_dacs",
+												"modules/wr_eca",
+												"modules/wr_tlu",
 												"modules/wrc_core" ],
                      "git" : "git://ohwr.org/hdl-core-lib/general-cores.git"
 						}
--- a/modules/wr_eca/xwr_eca_pkg.vhd
+++ b/modules/wr_eca/xwr_eca_pkg.vhd
@@ -2,6 +2,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+library work;
 use work.wishbone_pkg.all;
 use work.gencores_pkg.all;


--- a/modules/wr_tlu/Manifest.py
+++ b/modules/wr_tlu/Manifest.py
+files = ["wb_cores_pkg_gsi.vhd", "wb_timestamp_latch.vhd"]