Merge branch 'gsi'

Conflicts: modules/wr_endpoint/ep_clock_alignment_fifo.vhd

Merge branch 'gsi'
Conflicts: modules/wr_endpoint/ep_clock_alignment_fifo.vhd
c1e6807b · Wesley W. Terpstra · 87bdf89b · cd9960f3 · c1e6807b · 87bdf89b
Commit c1e6807b authored Sep 10, 2012 by Wesley W. Terpstra
39 changed files
--- a/modules/wr_eca/xwr_eca.vhd
+++ b/modules/wr_eca/xwr_eca.vhd
@@ -89,18 +89,20 @@ begin
      addr_width => logFifoLen,
      data_width => c_wishbone_data_width*4)
    port map(
-      rst_n_i  => rst_n_i,
-      w_clk_i  => clk_i,
-      w_rdy_o  => w_rdy,
-      w_en_i   => w_en,
-      w_data_i => w_data,
-      a_clk_i  => '0',
-      a_rdy_o  => open,
-      a_en_i   => '0',
-      r_clk_i  => clk_i,
-      r_rdy_o  => r_rdy,
-      r_en_i   => r_en,
-      r_data_o => r_data);
+      w_clk_i   => clk_i,
+      w_rst_n_i => rst_n_i,
+      w_rdy_o   => w_rdy,
+      w_en_i    => w_en,
+      w_data_i  => w_data,
+      a_clk_i   => '0',
+      a_rst_n_i => '0',
+      a_rdy_o   => open,
+      a_en_i    => '0',
+      r_clk_i   => clk_i,
+      r_rst_n_i => rst_n_i,
+      r_rdy_o   => r_rdy,
+      r_en_i    => r_en,
+      r_data_o  => r_data);
  w_data(c_wishbone_data_width*4-1 downto c_wishbone_data_width*3) <= r_utchi;
  w_data(c_wishbone_data_width*3-1 downto c_wishbone_data_width*2) <= r_utclo;
  w_data(c_wishbone_data_width*2-1 downto c_wishbone_data_width*1) <= r_cycle;

--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_1.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_1.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_10.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_10.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_11.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_11.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_12.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_12.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_13.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_13.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_14.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_14.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_15.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_15.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_16.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_16.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_2.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_2.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_3.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_3.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_4.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_4.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_5.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_5.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_6.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_6.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_7.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_7.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_8.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_8.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_9.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_example_top_tb_9.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_full_mem_model.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_full_mem_model.vhd
--- a/platform/altera/ddr3/testbench/ddr3_mem_mem_model.vhd
+++ b/platform/altera/ddr3/testbench/ddr3_mem_mem_model.vhd
--- a/syn/gsi_exploder/wr_core_demo/exploder_top.qsf
+++ b/syn/gsi_exploder/wr_core_demo/exploder_top.qsf
--- a/syn/gsi_pexaria2a/wr_core_demo/pexaria2a_top.qsf
+++ b/syn/gsi_pexaria2a/wr_core_demo/pexaria2a_top.qsf
--- a/syn/gsi_scu/wr_core_demo/scu.qsf
+++ b/syn/gsi_scu/wr_core_demo/scu.qsf
@@ -27,7 +27,7 @@ set_global_assignment -name DEVICE EP2AGX125EF29C5
 set_global_assignment -name TOP_LEVEL_ENTITY scu_top
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:00:25  FEBRUARY 13, 2012"
-set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
+set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1"
 set_global_assignment -name SEARCH_PATH ./
 set_global_assignment -name SEARCH_PATH "pci_express_compiler-library/"
 set_global_assignment -name SEARCH_PATH "pci_megacore-library/"
@@ -704,6 +704,10 @@ set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 3.47P -to DDR3
 set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.66N -to DDR3_ODT
 set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 3.47P -to DDR3_ODT
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DDR3_WE_n
+set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_reset.vhd"
+set_global_assignment -name VHDL_FILE "../../../ip_cores/etherbone-core/hdl/EB_SPEC_Test/etherbone_pkg.vhd"
+set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll_ng/spll_bangbang_pd.vhd
+set_global_assignment -name VHDL_FILE ../../../modules/wr_endpoint/ep_crc32_pkg.vhd
 set_global_assignment -name VHDL_FILE ../../../platform/altera/pow_reset.vhd
 set_global_assignment -name VHDL_FILE ../../../platform/altera/flash_loader.vhd
 set_global_assignment -name VHDL_FILE ../../../platform/altera/altera_pkg.vhd

--- a/syn/gsi_scu2/wr_core_demo/scu2.qsf
+++ b/syn/gsi_scu2/wr_core_demo/scu2.qsf
--- a/top/gsi_exploder/wr_core_demo/exploder_top.sdc
+++ b/top/gsi_exploder/wr_core_demo/exploder_top.sdc
 derive_pll_clocks -create_base_clocks
-
 derive_clock_uncertainty

-# connected to SOPC
-#create_clock -period 125Mhz -name F_PLL_6p [get_ports {F_PLL_6p}]
+# cut the clock domains from each other
+set_clock_groups -asynchronous \
+ -group { altera_reserved_tck                      } \
+ -group { clk_20m_vcxo_i       dmtd_clk_pll_inst|* } \
+ -group { clk_125m_pllref_p    sys_pll_inst|*      } \
+ -group { L_CLKp                                   } \
+ -group {                      wr_gxb_phy*         }

-create_clock -period 125Mhz -name clk_125m_pllref_p [get_ports {clk_125m_pllref_p}]
-create_clock -period 125Mhz -name L_CLKp [get_ports {L_CLKp}]
-create_clock -period 125Mhz -name F_PLL_6p [get_ports {F_PLL_6p}]
-create_clock -period 20Mhz -name clk_20m_vcxo_i [get_ports {clk_20m_vcxo_i}]
\ No newline at end of file
+# these paths are supposedly made safe by Tom's sync_ffs. i have my doubts, but ...
+set_false_path -from {xwr_core:U_WR_CORE|wr_core:WRPC|xwr_pps_gen:PPS_GEN|wr_pps_gen:WRAPPED_PPSGEN|adj_utc*} \
+               -to   {xwr_core:U_WR_CORE|wr_core:WRPC|xwr_pps_gen:PPS_GEN|wr_pps_gen:WRAPPED_PPSGEN|cntr_utc*}
--- a/top/gsi_exploder/wr_core_demo/exploder_top.vhd
+++ b/top/gsi_exploder/wr_core_demo/exploder_top.vhd
--- a/top/gsi_exploder/wr_core_demo/flash_loader.vhd
+++ b/top/gsi_exploder/wr_core_demo/flash_loader.vhd
--- a/top/gsi_exploder/wr_core_demo/pow_reset.vhd
+++ b/top/gsi_exploder/wr_core_demo/pow_reset.vhd
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity pow_reset is
-  port (
-    clk    : in  std_logic;             -- 125Mhz
-    nreset : buffer std_logic
-    );
-end entity;
-
-architecture pow_reset_arch of pow_reset is
-  
-  signal powerOn : unsigned(6 downto 0) := "0000000";  -- 7Bit for 1ms nrst
-  
-begin
-     
-     nres : process(Clk)
-     begin
-       if Clk'event and Clk = '1' then
-         if nreset = '0' then
-           powerOn <= powerOn + 1;
-       end if;
-
-       nReset <= std_logic(powerOn(powerON'high));
-     end if;
-end process;
-
-end architecture;
-
--- a/top/gsi_exploder/wr_core_demo/spec_serial_dac.vhd
+++ b/top/gsi_exploder/wr_core_demo/spec_serial_dac.vhd
--- a/top/gsi_exploder/wr_core_demo/spec_serial_dac_arb.vhd
+++ b/top/gsi_exploder/wr_core_demo/spec_serial_dac_arb.vhd
--- a/top/gsi_pexaria2a/wr_core_demo/pexaria2a.sdc
+++ b/top/gsi_pexaria2a/wr_core_demo/pexaria2a.sdc
--- a/top/gsi_pexaria2a/wr_core_demo/pexaria2a_top.vhd
+++ b/top/gsi_pexaria2a/wr_core_demo/pexaria2a_top.vhd
--- a/top/gsi_pexaria2a/wr_core_demo/pow_reset.vhd
+++ b/top/gsi_pexaria2a/wr_core_demo/pow_reset.vhd
--- a/top/gsi_pexaria2a/wr_core_demo/spec_serial_dac.vhd
+++ b/top/gsi_pexaria2a/wr_core_demo/spec_serial_dac.vhd
--- a/top/gsi_pexaria2a/wr_core_demo/spec_serial_dac_arb.vhd
+++ b/top/gsi_pexaria2a/wr_core_demo/spec_serial_dac_arb.vhd
--- a/top/gsi_scu/wr_core_demo/scu_top.sdc
+++ b/top/gsi_scu/wr_core_demo/scu_top.sdc
--- a/top/gsi_scu/wr_core_demo/scu_top.vhd
+++ b/top/gsi_scu/wr_core_demo/scu_top.vhd
--- a/top/gsi_scu2/wr_core_demo/scu_top.sdc
+++ b/top/gsi_scu2/wr_core_demo/scu_top.sdc
--- a/top/gsi_scu2/wr_core_demo/scu_top.vhd
+++ b/top/gsi_scu2/wr_core_demo/scu_top.vhd