Merge branch 'greg-zynq' into proposed_master

b2121252 · Grzegorz Daniluk · bcd1f0a3 · f99a845e · b2121252 · b2121252
Commit b2121252 authored Aug 25, 2017 by Grzegorz Daniluk
32 changed files
--- a/.gitignore
+++ b/.gitignore
@@ -17,3 +17,5 @@ doc/
 *.elf
 *.ucdb
 Makefile
+*.xml
+xgui/
--- a/bin/wrpc/wrc_phy16.bram
+++ b/bin/wrpc/wrc_phy16.bram
--- a/board/fasec/Manifest.py
+++ b/board/fasec/Manifest.py
+files = [
+    "wr_fasec_pkg.vhd",
+    "xwrc_board_fasec.vhd",
+    "wrc_board_fasec.vhd",
+    "wrc_board_fasec_ip.xdc"
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/fasec/component.xml
+++ b/board/fasec/component.xml
--- a/board/fasec/wr_fasec_pkg.vhd
+++ b/board/fasec/wr_fasec_pkg.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_board_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_fasec_pkg is
+
+  component xwrc_board_fasec
+    generic(
+      g_simulation                : integer              := 0;
+      g_with_external_clock_input : boolean              := TRUE;
+      g_aux_clks                  : integer              := 0;
+      g_fabric_iface              : t_board_fabric_iface := plain;
+      g_streamers_op_mode         : t_streamers_op_mode  := TX_AND_RX;
+      g_tx_streamer_params        : t_tx_streamer_params := c_tx_streamer_params_defaut;
+      g_rx_streamer_params        : t_rx_streamer_params := c_rx_streamer_params_defaut;
+      g_dpram_initf               : string               := "default_xilinx";
+      g_diag_id                   : integer              := 0;
+      g_diag_ver                  : integer              := 0;
+      g_diag_ro_size              : integer              := 0;
+      g_diag_rw_size              : integer              := 0);
+    port (
+      areset_n_i          : in  std_logic;
+      areset_edge_n_i     : in  std_logic := '1';
+      clk_20m_vcxo_i      : in  std_logic;
+      clk_125m_pllref_p_i : in  std_logic;
+      clk_125m_pllref_n_i : in  std_logic;
+      clk_125m_gtp_n_i    : in  std_logic;
+      clk_125m_gtp_p_i    : in  std_logic;
+      clk_aux_i           : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      clk_10m_ext_i       : in  std_logic                               := '0';
+      pps_ext_i           : in  std_logic                               := '0';
+      clk_sys_62m5_o      : out std_logic;
+      clk_ref_125m_o      : out std_logic;
+      rst_sys_62m5_n_o    : out std_logic;
+      rst_ref_125m_n_o    : out std_logic;
+  
+      plldac_sclk_o   : out std_logic;
+      plldac_din_o    : out std_logic;
+      pll25dac_cs_n_o : out std_logic;
+      pll20dac_cs_n_o : out std_logic;
+  
+      sfp_txp_o         : out std_logic;
+      sfp_txn_o         : out std_logic;
+      sfp_rxp_i         : in  std_logic;
+      sfp_rxn_i         : in  std_logic;
+      sfp_det_i         : in  std_logic := '1';
+      sfp_sda_b         : inout std_logic;
+      sfp_scl_b         : inout std_logic;
+      sfp_rate_select_o : out std_logic;
+      sfp_tx_fault_i    : in  std_logic := '0';
+      sfp_tx_disable_o  : out std_logic;
+      sfp_los_i         : in  std_logic := '0';
+  
+      eeprom_scl_b : inout std_logic;
+      eeprom_sda_b : inout std_logic;
+  
+      thermo_id : inout std_logic;
+      uart_rxd_i : in  std_logic;
+      uart_txd_o : out std_logic;
+  
+      flash_sclk_o : out std_logic;
+      flash_ncs_o  : out std_logic;
+      flash_mosi_o : out std_logic;
+      flash_miso_i : in  std_logic := '0';
+  
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      s00_axi_aclk_o  : out std_logic;
+      s00_axi_aresetn : in  std_logic;
+      s00_axi_awaddr  : in std_logic_vector(31 downto 0);
+      s00_axi_awprot  : in  std_logic_vector(2 downto 0);
+      s00_axi_awvalid : in  std_logic;
+      s00_axi_awready : out std_logic;
+      s00_axi_wdata   : in std_logic_vector(31 downto 0);
+      s00_axi_wstrb   : in std_logic_vector(3 downto 0);
+      s00_axi_wvalid  : in  std_logic;
+      s00_axi_wready  : out std_logic;
+      s00_axi_bresp   : out std_logic_vector(1 downto 0);
+      s00_axi_bvalid  : out std_logic;
+      s00_axi_bready  : in std_logic;
+      s00_axi_araddr  : in std_logic_vector(31 downto 0);
+      s00_axi_arprot  : in std_logic_vector(2 downto 0);
+      s00_axi_arvalid : in std_logic;
+      s00_axi_arready : out std_logic;
+      s00_axi_rdata   : out std_logic_vector(31 downto 0);
+      s00_axi_rresp   : out std_logic_vector(1 downto 0);
+      s00_axi_rvalid  : out std_logic;
+      s00_axi_rready  : in std_logic;
+      s00_axi_rlast   : out std_logic;
+      axi_int_o       : out std_logic;
+  
+      wrf_src_o : out t_wrf_source_out;
+      wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o : out t_wrf_sink_out;
+      wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+  
+      wrs_tx_data_i  : in  std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
+      wrs_tx_valid_i : in  std_logic                                        := '0';
+      wrs_tx_dreq_o  : out std_logic;
+      wrs_tx_last_i  : in  std_logic                                        := '1';
+      wrs_tx_flush_i : in  std_logic                                        := '0';
+      wrs_tx_cfg_i   : in  t_tx_streamer_cfg                                := c_tx_streamer_cfg_default;
+      wrs_rx_first_o : out std_logic;
+      wrs_rx_last_o  : out std_logic;
+      wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+      wrs_rx_valid_o : out std_logic;
+      wrs_rx_dreq_i  : in  std_logic                                        := '0';
+      wrs_rx_cfg_i   : in t_rx_streamer_cfg                                 := c_rx_streamer_cfg_default;
+
+      wb_eth_master_o : out t_wishbone_master_out;
+      wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      aux_diag_i : in  t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
+      aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
+  
+      tm_dac_value_o       : out std_logic_vector(23 downto 0);
+      tm_dac_wr_o          : out std_logic_vector(g_aux_clks-1 downto 0);
+      tm_clk_aux_lock_en_i : in  std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
+      tm_clk_aux_locked_o  : out std_logic_vector(g_aux_clks-1 downto 0);
+  
+      timestamps_o     : out t_txtsu_timestamp;
+      timestamps_ack_i : in  std_logic := '1';
+  
+      abscal_txts_o       : out std_logic;
+      abscal_rxts_o       : out std_logic;
+  
+      fc_tx_pause_req_i   : in  std_logic                     := '0';
+      fc_tx_pause_delay_i : in  std_logic_vector(15 downto 0) := x"0000";
+      fc_tx_pause_ready_o : out std_logic;
+  
+      tm_link_up_o    : out std_logic;
+      tm_time_valid_o : out std_logic;
+      tm_tai_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+  
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      btn1_i     : in  std_logic := '1';
+      btn2_i     : in  std_logic := '1';
+      pps_p_o    : out std_logic;
+      pps_led_o  : out std_logic;
+      link_ok_o  : out std_logic);
+  end component xwrc_board_fasec;
+
+end wr_fasec_pkg;
--- a/board/fasec/wrc_board_fasec.vhd
+++ b/board/fasec/wrc_board_fasec.vhd
--- a/board/fasec/wrc_board_fasec_ip.xdc
+++ b/board/fasec/wrc_board_fasec_ip.xdc
+create_clock -period 50.000 -name clk_20m_vcxo -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
+create_clock -period 8.000 -name clk_125m_pllref -waveform {0.000 4.000} [get_ports clk_125m_pllref_p_i]
+create_clock -period 8.000 -name clk_125m_gtp -waveform {0.000 4.000} [get_ports clk_125m_gtp_p_i]
+create_clock -period 100.000 -name clk_10m_ext -waveform {0.000 50.000} [get_ports clk_10m_ext_i]
+create_clock -period 16.000 -name clk_gtx_rx -waveform {0.000 8.000} [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
+create_generated_clock -name clk_gtx_tx -source [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtp_dedicated_clk/O] -divide_by 2 [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
+
+set_clock_groups -asynchronous -group [get_clocks clk_gtx_rx] -group [get_clocks [get_clocks -of_objects [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0]]]
+set_clock_groups -asynchronous -group [get_clocks clk_gtx_tx] -group [get_clocks [get_clocks -of_objects [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0]]]
+
+set_clock_groups -asynchronous -group [get_clocks clk_sys] -group [get_clocks clk_gtx_rx]
+
+
+
--- a/board/fasec/xwrc_board_fasec.vhd
+++ b/board/fasec/xwrc_board_fasec.vhd
--- a/general-cores @ ab1ee585
+++ b/general-cores @ ab1ee585
-Subproject commit 96295346bb6742b03b43930a4e8a5c73028f4572
+Subproject commit ab1ee585da28a69f863ba2939d5cf1257d074f2f
--- a/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+++ b/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ep_pcs_tbi_mdio_wb.vhd
 -- Author         : auto-generated by wbgen2 from pcs_regs.wb
-- Created        : Thu Aug  6 09:50:34 2015
+-- Created        : Wed Aug 16 22:43:42 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
@@ -120,22 +120,12 @@ signal mdio_ectrl_tx_prbs_sel_int               : std_logic_vector(2 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal bwsel_reg                                : std_logic_vector(3 downto 0);
 signal rwaddr_reg                               : std_logic_vector(4 downto 0);
 signal ack_in_progress                          : std_logic      ;
-signal wr_int                                   : std_logic      ;
-signal rd_int                                   : std_logic      ;
-signal allones                                  : std_logic_vector(31 downto 0);
-signal allzeros                                 : std_logic_vector(31 downto 0);

 begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
  wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
  process (clk_sys_i, rst_n_i)

--- a/modules/wr_endpoint/ep_registers_pkg.vhd
+++ b/modules/wr_endpoint/ep_registers_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ep_registers_pkg.vhd
 -- Author         : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created        : Thu Aug  6 15:57:28 2015
+-- Created        : Wed Aug 16 22:43:41 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb

--- a/modules/wr_endpoint/ep_wishbone_controller.vhd
+++ b/modules/wr_endpoint/ep_wishbone_controller.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ep_wishbone_controller.vhd
 -- Author         : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created        : Thu Aug  6 15:57:28 2015
+-- Created        : Wed Aug 16 22:43:41 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
@@ -83,22 +83,12 @@ signal ep_mdio_asr_phyad_int                    : std_logic_vector(7 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal bwsel_reg                                : std_logic_vector(3 downto 0);
 signal rwaddr_reg                               : std_logic_vector(4 downto 0);
 signal ack_in_progress                          : std_logic      ;
-signal wr_int                                   : std_logic      ;
-signal rd_int                                   : std_logic      ;
-signal allones                                  : std_logic_vector(31 downto 0);
-signal allzeros                                 : std_logic_vector(31 downto 0);

 begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
  wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
  process (clk_sys_i, rst_n_i)

--- a/modules/wr_mini_nic/minic_wb_slave.vhd
+++ b/modules/wr_mini_nic/minic_wb_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : minic_wb_slave.vhd
 -- Author         : auto-generated by wbgen2 from mini_nic.wb
-- Created        : Wed Oct 26 11:30:27 2016
+-- Created        : Wed Aug 16 22:41:57 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
@@ -65,22 +65,12 @@ signal irq_inputs_vector_int                    : std_logic_vector(2 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal bwsel_reg                                : std_logic_vector(3 downto 0);
 signal rwaddr_reg                               : std_logic_vector(4 downto 0);
 signal ack_in_progress                          : std_logic      ;
-signal wr_int                                   : std_logic      ;
-signal rd_int                                   : std_logic      ;
-signal allones                                  : std_logic_vector(31 downto 0);
-signal allzeros                                 : std_logic_vector(31 downto 0);

 begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
  wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
  process (clk_sys_i, rst_n_i)

--- a/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+++ b/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : minic_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from mini_nic.wb
-- Created        : Wed Oct 26 11:30:27 2016
+-- Created        : Wed Aug 16 22:41:57 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb

--- a/modules/wr_pps_gen/pps_gen_regs.h
+++ b/modules/wr_pps_gen/pps_gen_regs.h
@@ -3,7 +3,7 @@

  * File           : pps_gen_regs.h
  * Author         : auto-generated by wbgen2 from pps_gen_wb.wb
-  * Created        : Fri Feb 10 10:53:05 2017
+  * Created        : Wed Aug 16 22:41:09 2017
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb

--- a/modules/wr_pps_gen/pps_gen_wb.vhd
+++ b/modules/wr_pps_gen/pps_gen_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : pps_gen_wb.vhd
 -- Author         : auto-generated by wbgen2 from pps_gen_wb.wb
-- Created        : Fri Feb 10 10:53:05 2017
+-- Created        : Wed Aug 16 22:41:09 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
@@ -154,22 +154,12 @@ signal ppsg_escr_nsec_set_sync2                 : std_logic      ;
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal bwsel_reg                                : std_logic_vector(3 downto 0);
 signal rwaddr_reg                               : std_logic_vector(2 downto 0);
 signal ack_in_progress                          : std_logic      ;
-signal wr_int                                   : std_logic      ;
-signal rd_int                                   : std_logic      ;
-signal allones                                  : std_logic_vector(31 downto 0);
-signal allzeros                                 : std_logic_vector(31 downto 0);

 begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
  wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
  process (clk_sys_i, rst_n_i)

--- a/modules/wr_softpll_ng/spll_wb_slave.vhd
+++ b/modules/wr_softpll_ng/spll_wb_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : spll_wb_slave.vhd
 -- Author         : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created        : Thu Apr 20 16:40:20 2017
+-- Created        : Wed Aug 16 22:42:41 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
@@ -73,22 +73,12 @@ signal irq_inputs_vector_int                    : std_logic_vector(0 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal bwsel_reg                                : std_logic_vector(3 downto 0);
 signal rwaddr_reg                               : std_logic_vector(5 downto 0);
 signal ack_in_progress                          : std_logic      ;
-signal wr_int                                   : std_logic      ;
-signal rd_int                                   : std_logic      ;
-signal allones                                  : std_logic_vector(31 downto 0);
-signal allzeros                                 : std_logic_vector(31 downto 0);

 begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
  wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
  process (clk_sys_i, rst_n_i)

--- a/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+++ b/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : spll_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created        : Thu Apr 20 16:40:20 2017
+-- Created        : Wed Aug 16 22:42:41 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
@@ -165,10 +165,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
 variable tmp: std_logic_vector(x'length-1 downto 0);
 begin
 for i in 0 to x'length-1 loop
-if(x(i) = 'X' or x(i) = 'U') then
-tmp(i):= '0';
+if x(i) = '1' then
+tmp(i):= '1';
 else
-tmp(i):=x(i);
+tmp(i):= '0';
 end if; 
 end loop; 
 return tmp;

--- a/modules/wr_streamers/wr_streamers_wb.vhd
+++ b/modules/wr_streamers/wr_streamers_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wr_streamers_wb.vhd
 -- Author         : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created        : Tue Jun 20 08:53:54 2017
+-- Created        : Wed Aug 16 22:45:12 2017
 -- Version        : 0x00000001
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------

--- a/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
+++ b/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wr_streamers_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created        : Tue Jun 20 08:53:54 2017
+-- Created        : Wed Aug 16 22:45:12 2017
 -- Version        : 0x00000001
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
@@ -155,10 +155,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
 variable tmp: std_logic_vector(x'length-1 downto 0);
 begin
 for i in 0 to x'length-1 loop
-if(x(i) = 'X' or x(i) = 'U') then
-tmp(i):= '0';
+if x(i) = '1' then
+tmp(i):= '1';
 else
-tmp(i):=x(i);
+tmp(i):= '0';
 end if; 
 end loop; 
 return tmp;

--- a/modules/wr_tbi_phy/Manifest.py
+++ b/modules/wr_tbi_phy/Manifest.py
-files = [	"dec_8b10b.vhd",
-                "enc_8b10b.vhd",
+files = [	"enc_8b10b.vhd",
                "wr_tbi_phy.vhd",
                "disparity_gen_pkg.vhd" ];
--- a/modules/wr_tbi_phy/wr_tbi_phy.vhd
+++ b/modules/wr_tbi_phy/wr_tbi_phy.vhd
@@ -66,7 +66,7 @@ end wr_tbi_phy;

 architecture rtl of wr_tbi_phy is

-  component dec_8b10b
+  component gc_dec_8b10b
    port (
      clk_i       : in  std_logic;
      rst_n_i     : in  std_logic;
@@ -124,7 +124,7 @@ begin  -- rtl
    end if;
  end process;

-  U_DEC : dec_8b10b
+  U_DEC : gc_dec_8b10b
    port map (
      clk_i    => tbi_rbclk_i,
      rst_n_i  => rst_synced_rbclk_n,

--- a/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/platform/xilinx/wr_xilinx_pkg.vhd
@@ -106,6 +106,7 @@ package wr_xilinx_pkg is
    port (
      clk_gtx_i      : in  std_logic;
      tx_out_clk_o   : out std_logic;
+      tx_locked_o    : out std_logic;
      tx_data_i      : in  std_logic_vector(15 downto 0);
      tx_k_i         : in  std_logic_vector(1 downto 0);
      tx_disparity_o : out std_logic;
@@ -121,7 +122,8 @@ package wr_xilinx_pkg is
      pad_txn_o      : out std_logic;
      pad_txp_o      : out std_logic;
      pad_rxn_i      : in  std_logic := '0';
-      pad_rxp_i      : in  std_logic := '0');
+      pad_rxp_i      : in  std_logic := '0';
+      rdy_o          : out std_logic);
  end component;

 end wr_xilinx_pkg;
--- a/platform/xilinx/xwrc_platform_xilinx.vhd
+++ b/platform/xilinx/xwrc_platform_xilinx.vhd
--- a/syn/fasec_ref_design/build.tcl
+++ b/syn/fasec_ref_design/build.tcl
+# Create Vivado project
+source ./fasec_ref_design.tcl
+
+# Create block design
+source ../../top/fasec_ref_design/system_top.tcl
+
+# Generate the wrapper
+set design_name [get_bd_designs]
+make_wrapper -files [get_files $design_name.bd] -top -import
--- a/syn/fasec_ref_design/fasec_ref_design.tcl
+++ b/syn/fasec_ref_design/fasec_ref_design.tcl
+#
+# Vivado (TM) v2016.4 (64-bit)
+#
+# fasec_ref_design.tcl: Tcl script for re-creating project 'fasec_ref_design'
+#
+# Generated by Vivado on Fri Aug 18 11:05:12 CEST 2017
+# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (fasec_ref_design.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    <none>
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "/home/greg/wr/wr-cores/top/fasec_ref_design/fasec_ref_design.xdc"
+#
+#*****************************************************************************************
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+variable script_file
+set script_file "fasec_ref_design.tcl"
+
+# Help information for this script
+proc help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < [llength $::argc]} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
+      "--help"       { help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/"]"
+
+# Create project
+create_project fasec_ref_design . -part xc7z030ffg676-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Reconstruct message rules
+# None
+
+# Set project properties
+set obj [get_projects fasec_ref_design]
+set_property "corecontainer.enable" "1" $obj
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "ip_cache_permissions" "read write" $obj
+set_property "ip_output_repo" "/home/greg/wr/wr-cores/syn/fasec_ref_design/fasec_ref_design.cache/ip" $obj
+set_property "part" "xc7z030ffg676-2" $obj
+set_property "sim.ip.auto_export_scripts" "1" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "target_language" "VHDL" $obj
+set_property "xsim.array_display_limit" "64" $obj
+set_property "xsim.trace_limit" "65536" $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+set_property "ip_repo_paths" "[file normalize "$origin_dir/../../"]" $obj
+
+# Rebuild user ip_repo's index before adding any source files
+update_ip_catalog -rebuild
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Empty (no sources present)
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/../../top/fasec_ref_design/fasec_ref_design.xdc"]"
+set file_added [add_files -norecurse -fileset $obj $file]
+set file "$origin_dir/../../top/fasec_ref_design/fasec_ref_design.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property "file_type" "XDC" $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property "transport_int_delay" "0" $obj
+set_property "transport_path_delay" "0" $obj
+set_property "xelab.nosort" "1" $obj
+set_property "xelab.unifast" "" $obj
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+  create_run -name synth_1 -part xc7z030ffg676-2 -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2016" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property "needs_refresh" "1" $obj
+set_property "part" "xc7z030ffg676-2" $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+  create_run -name impl_1 -part xc7z030ffg676-2 -flow {Vivado Implementation 2016} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2016" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property "needs_refresh" "1" $obj
+set_property "part" "xc7z030ffg676-2" $obj
+set_property "steps.write_bitstream.args.readback_file" "0" $obj
+set_property "steps.write_bitstream.args.verbose" "0" $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:fasec_ref_design"
--- a/syn/wrc_board_fasec_ip/Manifest.py
+++ b/syn/wrc_board_fasec_ip/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc7z030"
+syn_grade = "-2"
+syn_package = "ffg676"
+
+syn_top = "wrc_board_fasec"
+syn_project = "wrc_board_fasec_ip"
+
+syn_tool = "vivado"
+
+modules = { "local" : [
+                "../../",
+                "../../board/fasec/" ] }
--- a/syn/wrc_board_fasec_ip/README.txt
+++ b/syn/wrc_board_fasec_ip/README.txt
+To create Vivado project for wrc_board_fasec IPcore generation, open Vivado and
+run build.tcl script.
--- a/syn/wrc_board_fasec_ip/build.tcl
+++ b/syn/wrc_board_fasec_ip/build.tcl
+# Copy component.xml
+file copy -force ../../board/fasec/component.xml ../../.
+
+# Run tcl script generated by Vivado
+source ./wrc_board_fasec_ip.tcl
--- a/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
+++ b/syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
--- a/top/fasec_ref_design/fasec_ref_design.xdc
+++ b/top/fasec_ref_design/fasec_ref_design.xdc
+set_property PACKAGE_PIN K11 [get_ports areset_n_i]
+set_property IOSTANDARD LVCMOS18 [get_ports areset_n_i]
+
+set_property PACKAGE_PIN C8 [get_ports clk_20m_vcxo_i]
+set_property IOSTANDARD LVCMOS18 [get_ports clk_20m_vcxo_i]
+set_property PACKAGE_PIN U5 [get_ports clk_125m_gtp_n_i]
+set_property PACKAGE_PIN U6 [get_ports clk_125m_gtp_p_i]
+#set_property IOSTANDARD LVDS_25 [get_ports clk_125m_pllref_p_i]
+set_property PACKAGE_PIN G7 [get_ports clk_125m_pllref_p_i]
+set_property PACKAGE_PIN F7 [get_ports clk_125m_pllref_n_i]
+#set_property IOSTANDARD LVDS_25 [get_ports clk_125m_pllref_n_i]
+
+
+set_property PACKAGE_PIN N6 [get_ports plldac_sclk_o]
+set_property IOSTANDARD LVCMOS18 [get_ports plldac_sclk_o]
+set_property PACKAGE_PIN K8 [get_ports plldac_din_o]
+set_property IOSTANDARD LVCMOS18 [get_ports plldac_din_o]
+set_property PACKAGE_PIN K7 [get_ports pll25dac_cs_n_o]
+set_property IOSTANDARD LVCMOS18 [get_ports pll25dac_cs_n_o]
+set_property PACKAGE_PIN N7 [get_ports pll20dac_cs_n_o]
+set_property IOSTANDARD LVCMOS18 [get_ports pll20dac_cs_n_o]
+
+set_property PACKAGE_PIN J14 [get_ports eeprom_sda_b]
+set_property IOSTANDARD LVCMOS18 [get_ports eeprom_sda_b]
+set_property SLEW FAST [get_ports eeprom_sda_b]
+set_property PACKAGE_PIN H14 [get_ports eeprom_scl_b]
+set_property IOSTANDARD LVCMOS18 [get_ports eeprom_scl_b]
+set_property SLEW FAST [get_ports eeprom_scl_b]
+
+set_property PACKAGE_PIN K10 [get_ports thermo_id]
+set_property IOSTANDARD LVCMOS18 [get_ports thermo_id]
+
+set_property IOSTANDARD LVCMOS25 [get_ports SFP_sda]
+set_property PACKAGE_PIN AB17 [get_ports SFP_sda]
+set_property PACKAGE_PIN G16 [get_ports SFP_rx_los]
+set_property IOSTANDARD LVCMOS18 [get_ports SFP_rx_los]
+set_property PACKAGE_PIN V4 [get_ports SFP_rxp]
+set_property PACKAGE_PIN K15 [get_ports SFP_tx_fault]
+set_property IOSTANDARD LVCMOS18 [get_ports SFP_tx_fault]
+set_property PACKAGE_PIN AB16 [get_ports SFP_scl]
+set_property IOSTANDARD LVCMOS25 [get_ports SFP_scl]
+set_property PACKAGE_PIN J15 [get_ports SFP_mod_abs]
+set_property IOSTANDARD LVCMOS18 [get_ports SFP_mod_abs]
+set_property PACKAGE_PIN G14 [get_ports sfp_rate_select_o]
+set_property IOSTANDARD LVCMOS18 [get_ports sfp_rate_select_o]
+set_property PACKAGE_PIN G15 [get_ports SFP_tx_disable]
+set_property IOSTANDARD LVCMOS18 [get_ports SFP_tx_disable]
+set_property IOSTANDARD LVDS [get_ports clk_125m_pllref_p_i]
+
+set_property PACKAGE_PIN AC18 [get_ports {pps_p[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {pps_p[0]}]
+set_property PACKAGE_PIN AB26 [get_ports {clk_sys_62m5_p[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {clk_sys_62m5_p[0]}]
+set_property PACKAGE_PIN AE10 [get_ports {clk_ref_125m_p[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {clk_ref_125m_p[0]}]
+
+set_property PACKAGE_PIN AB22 [get_ports {dio_term[0]}]
+set_property PACKAGE_PIN AB10 [get_ports {dio_term[1]}]
+set_property PACKAGE_PIN Y13 [get_ports {dio_term[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_term[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_term[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_term[2]}]
+
+set_property PACKAGE_PIN AB21 [get_ports {dio_oe_n[0]}]
+set_property PACKAGE_PIN AD26 [get_ports {dio_oe_n[1]}]
+set_property PACKAGE_PIN AF17 [get_ports {dio_oe_n[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[2]}]
+
+
+set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_sys]
--- a/top/fasec_ref_design/system_top.tcl
+++ b/top/fasec_ref_design/system_top.tcl