BUFG and BUFIO2 standard Xilinx components don't need declarations

This also removes Xilinx ISE synthesis warnings like: wr-cores\platform\xilinx\wr_gtp_phy\wr_gtp_phy_spartan6.vhd" Line 246: <bufio2> remains a black-box since it has no binding entity.

BUFG and BUFIO2 standard Xilinx components don't need declarations
This also removes Xilinx ISE synthesis warnings like: wr-cores\platform\xilinx\wr_gtp_phy\wr_gtp_phy_spartan6.vhd" Line 246: <bufio2> remains a black-box since it has no binding entity.
bad54c60 · Grzegorz Daniluk · 3c2a6c72 · bad54c60
Commit bad54c60 authored Jan 24, 2017 by Grzegorz Daniluk
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wr_gtp_phy_spartan6.vhd platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd +1 -20

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--- a/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
@@ -46,7 +46,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 library unisim;
-use unisim.all;
+use unisim.vcomponents.all;

 library work;
 use work.gencores_pkg.all;
@@ -237,25 +237,6 @@ architecture rtl of wr_gtp_phy_spartan6 is
      TXENPRBSTST1_IN       : in  std_logic_vector(2 downto 0));
  end component;

-  component BUFG
-    port (
-      O : out std_ulogic;
-      I : in  std_ulogic);
-  end component;
-
-  component BUFIO2
-    generic (
-      DIVIDE_BYPASS : boolean := true;
-      DIVIDE        : integer := 1;
-      I_INVERT      : boolean := false;
-      USE_DOUBLER   : boolean := false);
-    port (
-      DIVCLK       : out std_ulogic;
-      IOCLK        : out std_ulogic;
-      SERDESSTROBE : out std_ulogic;
-      I            : in  std_ulogic);
-  end component;
-
  component gtp_phase_align
    generic(
      g_simulation : integer);