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White Rabbit core collection
Commit c6059955 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
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[streamers/review] renamed xwr_transmission to xwr_streamers and removed gc_ 

the name of the top entity in the wr_streamers folder was missleading
(xwr_transmission). It was recommended to rename, which I did.
Additionally, names of two modules in wr_streamers start with gc_
which could indicate they are general-cores. This is not the case,
moreover the entity names did not have gc_. I removed the gc_
parent 73531de1
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Showing with 294 additions and 294 deletions
board/common/xwrc_board_common.vhd
View file @ c6059955
...@@ -423,7 +423,7 @@ begin -- architecture struct ...@@ -423,7 +423,7 @@ begin -- architecture struct
gen_wr_streamers : if (g_fabric_iface = STREAMERS) generate gen_wr_streamers : if (g_fabric_iface = STREAMERS) generate
cmp_xwr_transmission : xwr_transmission cmp_xwr_streamers : xwr_streamers
generic map ( generic map (
g_streamers_op_mode => g_streamers_op_mode, g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params, g_tx_streamer_params => g_tx_streamer_params,
......
modules/wr_streamers/Manifest.py
View file @ c6059955
...@@ -4,12 +4,12 @@ files = ["streamers_pkg.vhd", ...@@ -4,12 +4,12 @@ files = ["streamers_pkg.vhd",
"tx_streamer.vhd", "tx_streamer.vhd",
"xrx_streamer.vhd", "xrx_streamer.vhd",
"rx_streamer.vhd", "rx_streamer.vhd",
"gc_escape_inserter.vhd", "escape_inserter.vhd",
"gc_escape_detector.vhd", "escape_detector.vhd",
"dropping_buffer.vhd", "dropping_buffer.vhd",
"wr_transmission_wbgen2_pkg.vhd", "wr_streamers_wbgen2_pkg.vhd",
"xwr_transmission.vhd", "xwr_streamers.vhd",
"wr_transmission_wb.vhd", "wr_streamers_wb.vhd",
"streamers_priv_pkg.vhd", "streamers_priv_pkg.vhd",
"xtx_streamers_stats.vhd", "xtx_streamers_stats.vhd",
"xrx_streamers_stats.vhd" "xrx_streamers_stats.vhd"
......
modules/wr_streamers/build_wb.sh
View file @ c6059955
#!/bin/bash #!/bin/bash
mkdir -p doc mkdir -p doc
wbgen2 -C ./doc/wr_transmission.h -D ./doc/wr_transmission_wb.html -p wr_transmission_wbgen2_pkg.vhd -H record -V wr_transmission_wb.vhd --cstyle defines --lang vhdl -K ../../sim/wr_transmission_wb.svh wr_transmission_wb.wb wbgen2 -C ./doc/wr_streamers.h -D ./doc/wr_streamers_wb.html -p wr_streamers_wbgen2_pkg.vhd -H record -V wr_streamers_wb.vhd --cstyle defines --lang vhdl -K ../../sim/wr_streamers_wb.svh wr_streamers_wb.wb
\ No newline at end of file \ No newline at end of file
modules/wr_streamers/streamers_pkg.vhd
View file @ c6059955
...@@ -266,7 +266,7 @@ package streamers_pkg is ...@@ -266,7 +266,7 @@ package streamers_pkg is
constant c_WR_TRANS_ARR_SIZE_OUT : integer := c_STREAMERS_ARR_SIZE_OUT+3; constant c_WR_TRANS_ARR_SIZE_OUT : integer := c_STREAMERS_ARR_SIZE_OUT+3;
constant c_WR_TRANS_ARR_SIZE_IN : integer := c_STREAMERS_ARR_SIZE_IN; constant c_WR_TRANS_ARR_SIZE_IN : integer := c_STREAMERS_ARR_SIZE_IN;
component xwr_transmission is component xwr_streamers is
generic ( generic (
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX; g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
--tx/rx --tx/rx
......
modules/wr_streamers/streamers_priv_pkg.vhd
View file @ c6059955
...@@ -40,7 +40,7 @@ use ieee.std_logic_1164.all; ...@@ -40,7 +40,7 @@ use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
use work.wishbone_pkg.all; -- needed for t_wishbone_slave_in, etc use work.wishbone_pkg.all; -- needed for t_wishbone_slave_in, etc
use work.streamers_pkg.all; use work.streamers_pkg.all;
use work.wr_transmission_wbgen2_pkg.all; use work.wr_streamers_wbgen2_pkg.all;
package streamers_priv_pkg is package streamers_priv_pkg is
...@@ -82,7 +82,7 @@ package streamers_priv_pkg is ...@@ -82,7 +82,7 @@ package streamers_priv_pkg is
latency_min_o : out std_logic_vector(27 downto 0)); latency_min_o : out std_logic_vector(27 downto 0));
end component; end component;
component wr_transmission_wb is component wr_streamers_wb is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
...@@ -95,8 +95,8 @@ package streamers_priv_pkg is ...@@ -95,8 +95,8 @@ package streamers_priv_pkg is
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
regs_i : in t_wr_transmission_in_registers; regs_i : in t_wr_streamers_in_registers;
regs_o : out t_wr_transmission_out_registers regs_o : out t_wr_streamers_out_registers
); );
end component; end component;
......
modules/wr_streamers/wr_transmission_wb.wb → modules/wr_streamers/wr_streamers_wb.wb
View file @ c6059955
...@@ -27,8 +27,8 @@ peripheral { ...@@ -27,8 +27,8 @@ peripheral {
Public License along with this source; if not, download it \ Public License along with this source; if not, download it \
from http://www.gnu.org/licenses/lgpl-2.1.html \ from http://www.gnu.org/licenses/lgpl-2.1.html \
-----------------------------------------------------------------"; -----------------------------------------------------------------";
prefix = "wr_transmission"; prefix = "wr_streamers";
hdl_entity = "wr_transmission_wb"; hdl_entity = "wr_streamers_wb";
reg { reg {
name = "Statistics status and ctrl register"; name = "Statistics status and ctrl register";
......
modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd → modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @ c6059955
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Transmission control, status and debug -- Title : Wishbone slave core for WR Transmission control, status and debug
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wr_transmission_wbgen2_pkg.vhd -- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb -- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed Nov 30 10:02:17 2016 -- Created : Fri Apr 21 18:02:12 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -14,12 +14,12 @@ library ieee; ...@@ -14,12 +14,12 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
package wr_transmission_wbgen2_pkg is package wr_streamers_wbgen2_pkg is
-- Input registers (user design -> WB slave) -- Input registers (user design -> WB slave)
type t_wr_transmission_in_registers is record type t_wr_streamers_in_registers is record
sscr1_rx_latency_acc_overflow_i : std_logic; sscr1_rx_latency_acc_overflow_i : std_logic;
sscr1_rst_ts_cyc_i : std_logic_vector(27 downto 0); sscr1_rst_ts_cyc_i : std_logic_vector(27 downto 0);
sscr2_rst_ts_tai_lsb_i : std_logic_vector(31 downto 0); sscr2_rst_ts_tai_lsb_i : std_logic_vector(31 downto 0);
...@@ -38,7 +38,7 @@ package wr_transmission_wbgen2_pkg is ...@@ -38,7 +38,7 @@ package wr_transmission_wbgen2_pkg is
dummy_dummy_i : std_logic_vector(31 downto 0); dummy_dummy_i : std_logic_vector(31 downto 0);
end record; end record;
constant c_wr_transmission_in_registers_init_value: t_wr_transmission_in_registers := ( constant c_wr_streamers_in_registers_init_value: t_wr_streamers_in_registers := (
sscr1_rx_latency_acc_overflow_i => '0', sscr1_rx_latency_acc_overflow_i => '0',
sscr1_rst_ts_cyc_i => (others => '0'), sscr1_rst_ts_cyc_i => (others => '0'),
sscr2_rst_ts_tai_lsb_i => (others => '0'), sscr2_rst_ts_tai_lsb_i => (others => '0'),
...@@ -59,7 +59,7 @@ package wr_transmission_wbgen2_pkg is ...@@ -59,7 +59,7 @@ package wr_transmission_wbgen2_pkg is
-- Output registers (WB slave -> user design) -- Output registers (WB slave -> user design)
type t_wr_transmission_out_registers is record type t_wr_streamers_out_registers is record
sscr1_rst_stats_o : std_logic; sscr1_rst_stats_o : std_logic;
sscr1_rst_seq_id_o : std_logic; sscr1_rst_seq_id_o : std_logic;
sscr1_snapshot_stats_o : std_logic; sscr1_snapshot_stats_o : std_logic;
...@@ -89,7 +89,7 @@ package wr_transmission_wbgen2_pkg is ...@@ -89,7 +89,7 @@ package wr_transmission_wbgen2_pkg is
dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0); dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0);
end record; end record;
constant c_wr_transmission_out_registers_init_value: t_wr_transmission_out_registers := ( constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := (
sscr1_rst_stats_o => '0', sscr1_rst_stats_o => '0',
sscr1_rst_seq_id_o => '0', sscr1_rst_seq_id_o => '0',
sscr1_snapshot_stats_o => '0', sscr1_snapshot_stats_o => '0',
...@@ -118,12 +118,12 @@ package wr_transmission_wbgen2_pkg is ...@@ -118,12 +118,12 @@ package wr_transmission_wbgen2_pkg is
dbg_ctrl_mux_o => '0', dbg_ctrl_mux_o => '0',
dbg_ctrl_start_byte_o => (others => '0') dbg_ctrl_start_byte_o => (others => '0')
); );
function "or" (left, right: t_wr_transmission_in_registers) return t_wr_transmission_in_registers; function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers;
function f_x_to_zero (x:std_logic) return std_logic; function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector; function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package; end package;
package body wr_transmission_wbgen2_pkg is package body wr_streamers_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is function f_x_to_zero (x:std_logic) return std_logic is
begin begin
if x = '1' then if x = '1' then
...@@ -144,8 +144,8 @@ end if; ...@@ -144,8 +144,8 @@ end if;
end loop; end loop;
return tmp; return tmp;
end function; end function;
function "or" (left, right: t_wr_transmission_in_registers) return t_wr_transmission_in_registers is function "or" (left, right: t_wr_streamers_in_registers) return t_wr_streamers_in_registers is
variable tmp: t_wr_transmission_in_registers; variable tmp: t_wr_streamers_in_registers;
begin begin
tmp.sscr1_rx_latency_acc_overflow_i := f_x_to_zero(left.sscr1_rx_latency_acc_overflow_i) or f_x_to_zero(right.sscr1_rx_latency_acc_overflow_i); tmp.sscr1_rx_latency_acc_overflow_i := f_x_to_zero(left.sscr1_rx_latency_acc_overflow_i) or f_x_to_zero(right.sscr1_rx_latency_acc_overflow_i);
tmp.sscr1_rst_ts_cyc_i := f_x_to_zero(left.sscr1_rst_ts_cyc_i) or f_x_to_zero(right.sscr1_rst_ts_cyc_i); tmp.sscr1_rst_ts_cyc_i := f_x_to_zero(left.sscr1_rst_ts_cyc_i) or f_x_to_zero(right.sscr1_rst_ts_cyc_i);
......
modules/wr_streamers/xwr_transmission.vhd → modules/wr_streamers/xwr_streamers.vhd
View file @ c6059955
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
-- Project : WR Streamers -- Project : WR Streamers
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers -- URL : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : xwr_transmission.vhd -- File : xwr_streamers.vhd (renamed from xwr_transmission.vhd)
-- Author : Maciej Lipinski -- Author : Maciej Lipinski
-- Company : CERN -- Company : CERN
-- Platform : FPGA-generics -- Platform : FPGA-generics
...@@ -62,10 +62,10 @@ use work.wishbone_pkg.all; -- needed for t_wishbone_slave_in, etc ...@@ -62,10 +62,10 @@ use work.wishbone_pkg.all; -- needed for t_wishbone_slave_in, etc
use work.streamers_pkg.all; -- needed for streamers and c_WR_TRANS_ARR_SIZE_* use work.streamers_pkg.all; -- needed for streamers and c_WR_TRANS_ARR_SIZE_*
use work.wr_fabric_pkg.all; -- needed for :t_wrf_source_in, etc use work.wr_fabric_pkg.all; -- needed for :t_wrf_source_in, etc
use work.wrcore_pkg.all; -- needed for t_generic_word_array use work.wrcore_pkg.all; -- needed for t_generic_word_array
use work.wr_transmission_wbgen2_pkg.all; use work.wr_streamers_wbgen2_pkg.all;
use work.streamers_priv_pkg.all; use work.streamers_priv_pkg.all;
entity xwr_transmission is entity xwr_streamers is
generic ( generic (
-- Indicates whether this module instantiates both streamers (rx and tx) or only one -- Indicates whether this module instantiates both streamers (rx and tx) or only one
-- of them. An application that only receives or only transmits might want to use -- of them. An application that only receives or only transmits might want to use
...@@ -164,12 +164,12 @@ entity xwr_transmission is ...@@ -164,12 +164,12 @@ entity xwr_transmission is
rx_streamer_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default rx_streamer_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default
); );
end xwr_transmission; end xwr_streamers;
architecture rtl of xwr_transmission is architecture rtl of xwr_streamers is
signal to_wb : t_wr_transmission_in_registers; signal to_wb : t_wr_streamers_in_registers;
signal from_wb : t_wr_transmission_out_registers; signal from_wb : t_wr_streamers_out_registers;
signal dbg_word : std_logic_vector(31 downto 0); signal dbg_word : std_logic_vector(31 downto 0);
signal start_bit : std_logic_vector(from_wb.dbg_ctrl_start_byte_o'length-1+3 downto 0); signal start_bit : std_logic_vector(from_wb.dbg_ctrl_start_byte_o'length-1+3 downto 0);
signal rx_data : std_logic_vector(g_rx_streamer_params.data_width-1 downto 0); signal rx_data : std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
...@@ -336,7 +336,7 @@ begin ...@@ -336,7 +336,7 @@ begin
master_i => wb_regs_slave_out, master_i => wb_regs_slave_out,
master_o => wb_regs_slave_in); master_o => wb_regs_slave_in);
U_WB: wr_transmission_wb U_WB: wr_streamers_wb
port map ( port map (
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
......
sim/wr_streamers_wb.svh 0 → 100644
View file @ c6059955
`define ADDR_WR_STREAMERS_SSCR1 7'h0
`define WR_STREAMERS_SSCR1_RST_STATS_OFFSET 0
`define WR_STREAMERS_SSCR1_RST_STATS 32'h00000001
`define WR_STREAMERS_SSCR1_RST_SEQ_ID_OFFSET 1
`define WR_STREAMERS_SSCR1_RST_SEQ_ID 32'h00000002
`define WR_STREAMERS_SSCR1_SNAPSHOT_STATS_OFFSET 2
`define WR_STREAMERS_SSCR1_SNAPSHOT_STATS 32'h00000004
`define WR_STREAMERS_SSCR1_RX_LATENCY_ACC_OVERFLOW_OFFSET 3
`define WR_STREAMERS_SSCR1_RX_LATENCY_ACC_OVERFLOW 32'h00000008
`define WR_STREAMERS_SSCR1_RST_TS_CYC_OFFSET 4
`define WR_STREAMERS_SSCR1_RST_TS_CYC 32'hfffffff0
`define ADDR_WR_STREAMERS_SSCR2 7'h4
`define WR_STREAMERS_SSCR2_RST_TS_TAI_LSB_OFFSET 0
`define WR_STREAMERS_SSCR2_RST_TS_TAI_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_STAT 7'h8
`define WR_STREAMERS_TX_STAT_TX_SENT_CNT_OFFSET 0
`define WR_STREAMERS_TX_STAT_TX_SENT_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT1 7'hc
`define WR_STREAMERS_RX_STAT1_RX_RCVD_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT1_RX_RCVD_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT2 7'h10
`define WR_STREAMERS_RX_STAT2_RX_LOSS_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT2_RX_LOSS_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT3 7'h14
`define WR_STREAMERS_RX_STAT3_RX_LATENCY_MAX_OFFSET 0
`define WR_STREAMERS_RX_STAT3_RX_LATENCY_MAX 32'h0fffffff
`define ADDR_WR_STREAMERS_RX_STAT4 7'h18
`define WR_STREAMERS_RX_STAT4_RX_LATENCY_MIN_OFFSET 0
`define WR_STREAMERS_RX_STAT4_RX_LATENCY_MIN 32'h0fffffff
`define ADDR_WR_STREAMERS_RX_STAT5 7'h1c
`define WR_STREAMERS_RX_STAT5_RX_LATENCY_ACC_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT5_RX_LATENCY_ACC_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT6 7'h20
`define WR_STREAMERS_RX_STAT6_RX_LATENCY_ACC_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT6_RX_LATENCY_ACC_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT7 7'h24
`define WR_STREAMERS_RX_STAT7_RX_LATENCY_ACC_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT7_RX_LATENCY_ACC_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT8 7'h28
`define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_OFFSET 0
`define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG0 7'h2c
`define WR_STREAMERS_TX_CFG0_ETHERTYPE_OFFSET 0
`define WR_STREAMERS_TX_CFG0_ETHERTYPE 32'h0000ffff
`define ADDR_WR_STREAMERS_TX_CFG1 7'h30
`define WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG2 7'h34
`define WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_TX_CFG3 7'h38
`define WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB_OFFSET 0
`define WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG4 7'h3c
`define WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB_OFFSET 0
`define WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG0 7'h40
`define WR_STREAMERS_RX_CFG0_ETHERTYPE_OFFSET 0
`define WR_STREAMERS_RX_CFG0_ETHERTYPE 32'h0000ffff
`define WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST_OFFSET 16
`define WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST 32'h00010000
`define WR_STREAMERS_RX_CFG0_FILTER_REMOTE_OFFSET 17
`define WR_STREAMERS_RX_CFG0_FILTER_REMOTE 32'h00020000
`define ADDR_WR_STREAMERS_RX_CFG1 7'h44
`define WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG2 7'h48
`define WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG3 7'h4c
`define WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB_OFFSET 0
`define WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG4 7'h50
`define WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB_OFFSET 0
`define WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG5 7'h54
`define WR_STREAMERS_RX_CFG5_FIXED_LATENCY_OFFSET 0
`define WR_STREAMERS_RX_CFG5_FIXED_LATENCY 32'h0fffffff
`define ADDR_WR_STREAMERS_CFG 7'h58
`define WR_STREAMERS_CFG_OR_TX_ETHTYPE_OFFSET 0
`define WR_STREAMERS_CFG_OR_TX_ETHTYPE 32'h00000001
`define WR_STREAMERS_CFG_OR_TX_MAC_LOC_OFFSET 1
`define WR_STREAMERS_CFG_OR_TX_MAC_LOC 32'h00000002
`define WR_STREAMERS_CFG_OR_TX_MAC_TAR_OFFSET 2
`define WR_STREAMERS_CFG_OR_TX_MAC_TAR 32'h00000004
`define WR_STREAMERS_CFG_OR_RX_ETHERTYPE_OFFSET 16
`define WR_STREAMERS_CFG_OR_RX_ETHERTYPE 32'h00010000
`define WR_STREAMERS_CFG_OR_RX_MAC_LOC_OFFSET 17
`define WR_STREAMERS_CFG_OR_RX_MAC_LOC 32'h00020000
`define WR_STREAMERS_CFG_OR_RX_MAC_REM_OFFSET 18
`define WR_STREAMERS_CFG_OR_RX_MAC_REM 32'h00040000
`define WR_STREAMERS_CFG_OR_RX_ACC_BROADCAST_OFFSET 19
`define WR_STREAMERS_CFG_OR_RX_ACC_BROADCAST 32'h00080000
`define WR_STREAMERS_CFG_OR_RX_FTR_REMOTE_OFFSET 20
`define WR_STREAMERS_CFG_OR_RX_FTR_REMOTE 32'h00100000
`define WR_STREAMERS_CFG_OR_RX_FIX_LAT_OFFSET 21
`define WR_STREAMERS_CFG_OR_RX_FIX_LAT 32'h00200000
`define ADDR_WR_STREAMERS_DBG_CTRL 7'h5c
`define WR_STREAMERS_DBG_CTRL_MUX_OFFSET 0
`define WR_STREAMERS_DBG_CTRL_MUX 32'h00000001
`define WR_STREAMERS_DBG_CTRL_START_BYTE_OFFSET 8
`define WR_STREAMERS_DBG_CTRL_START_BYTE 32'h0000ff00
`define ADDR_WR_STREAMERS_DBG_DATA 7'h60
`define ADDR_WR_STREAMERS_DBG_RX_BVALUE 7'h64
`define ADDR_WR_STREAMERS_DBG_TX_BVALUE 7'h68
`define ADDR_WR_STREAMERS_DUMMY 7'h6c
`define WR_STREAMERS_DUMMY_DUMMY_OFFSET 0
`define WR_STREAMERS_DUMMY_DUMMY 32'hffffffff
sim/wr_transmission_wb.svh deleted 100644 → 0
View file @ 73531de1
`define ADDR_WR_TRANSMISSION_SSCR1 7'h0
`define WR_TRANSMISSION_SSCR1_RST_STATS_OFFSET 0
`define WR_TRANSMISSION_SSCR1_RST_STATS 32'h00000001
`define WR_TRANSMISSION_SSCR1_RST_SEQ_ID_OFFSET 1
`define WR_TRANSMISSION_SSCR1_RST_SEQ_ID 32'h00000002
`define WR_TRANSMISSION_SSCR1_SNAPSHOT_STATS_OFFSET 2
`define WR_TRANSMISSION_SSCR1_SNAPSHOT_STATS 32'h00000004
`define WR_TRANSMISSION_SSCR1_RX_LATENCY_ACC_OVERFLOW_OFFSET 3
`define WR_TRANSMISSION_SSCR1_RX_LATENCY_ACC_OVERFLOW 32'h00000008
`define WR_TRANSMISSION_SSCR1_RST_TS_CYC_OFFSET 4
`define WR_TRANSMISSION_SSCR1_RST_TS_CYC 32'hfffffff0
`define ADDR_WR_TRANSMISSION_SSCR2 7'h4
`define WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB_OFFSET 0
`define WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_TX_STAT 7'h8
`define WR_TRANSMISSION_TX_STAT_TX_SENT_CNT_OFFSET 0
`define WR_TRANSMISSION_TX_STAT_TX_SENT_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT1 7'hc
`define WR_TRANSMISSION_RX_STAT1_RX_RCVD_CNT_OFFSET 0
`define WR_TRANSMISSION_RX_STAT1_RX_RCVD_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT2 7'h10
`define WR_TRANSMISSION_RX_STAT2_RX_LOSS_CNT_OFFSET 0
`define WR_TRANSMISSION_RX_STAT2_RX_LOSS_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT3 7'h14
`define WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX_OFFSET 0
`define WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX 32'h0fffffff
`define ADDR_WR_TRANSMISSION_RX_STAT4 7'h18
`define WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN_OFFSET 0
`define WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN 32'h0fffffff
`define ADDR_WR_TRANSMISSION_RX_STAT5 7'h1c
`define WR_TRANSMISSION_RX_STAT5_RX_LATENCY_ACC_LSB_OFFSET 0
`define WR_TRANSMISSION_RX_STAT5_RX_LATENCY_ACC_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT6 7'h20
`define WR_TRANSMISSION_RX_STAT6_RX_LATENCY_ACC_MSB_OFFSET 0
`define WR_TRANSMISSION_RX_STAT6_RX_LATENCY_ACC_MSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT7 7'h24
`define WR_TRANSMISSION_RX_STAT7_RX_LATENCY_ACC_CNT_OFFSET 0
`define WR_TRANSMISSION_RX_STAT7_RX_LATENCY_ACC_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT8 7'h28
`define WR_TRANSMISSION_RX_STAT8_RX_LOST_BLOCK_CNT_OFFSET 0
`define WR_TRANSMISSION_RX_STAT8_RX_LOST_BLOCK_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_TX_CFG0 7'h2c
`define WR_TRANSMISSION_TX_CFG0_ETHERTYPE_OFFSET 0
`define WR_TRANSMISSION_TX_CFG0_ETHERTYPE 32'h0000ffff
`define ADDR_WR_TRANSMISSION_TX_CFG1 7'h30
`define WR_TRANSMISSION_TX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_TRANSMISSION_TX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_TX_CFG2 7'h34
`define WR_TRANSMISSION_TX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_TRANSMISSION_TX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_TRANSMISSION_TX_CFG3 7'h38
`define WR_TRANSMISSION_TX_CFG3_MAC_TARGET_LSB_OFFSET 0
`define WR_TRANSMISSION_TX_CFG3_MAC_TARGET_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_TX_CFG4 7'h3c
`define WR_TRANSMISSION_TX_CFG4_MAC_TARGET_MSB_OFFSET 0
`define WR_TRANSMISSION_TX_CFG4_MAC_TARGET_MSB 32'h0000ffff
`define ADDR_WR_TRANSMISSION_RX_CFG0 7'h40
`define WR_TRANSMISSION_RX_CFG0_ETHERTYPE_OFFSET 0
`define WR_TRANSMISSION_RX_CFG0_ETHERTYPE 32'h0000ffff
`define WR_TRANSMISSION_RX_CFG0_ACCEPT_BROADCAST_OFFSET 16
`define WR_TRANSMISSION_RX_CFG0_ACCEPT_BROADCAST 32'h00010000
`define WR_TRANSMISSION_RX_CFG0_FILTER_REMOTE_OFFSET 17
`define WR_TRANSMISSION_RX_CFG0_FILTER_REMOTE 32'h00020000
`define ADDR_WR_TRANSMISSION_RX_CFG1 7'h44
`define WR_TRANSMISSION_RX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_TRANSMISSION_RX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_CFG2 7'h48
`define WR_TRANSMISSION_RX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_TRANSMISSION_RX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_TRANSMISSION_RX_CFG3 7'h4c
`define WR_TRANSMISSION_RX_CFG3_MAC_REMOTE_LSB_OFFSET 0
`define WR_TRANSMISSION_RX_CFG3_MAC_REMOTE_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_CFG4 7'h50
`define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB_OFFSET 0
`define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB 32'h0000ffff
`define ADDR_WR_TRANSMISSION_RX_CFG5 7'h54
`define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY_OFFSET 0
`define WR_TRANSMISSION_RX_CFG5_FIXED_LATENCY 32'h0fffffff
`define ADDR_WR_TRANSMISSION_CFG 7'h58
`define WR_TRANSMISSION_CFG_OR_TX_ETHTYPE_OFFSET 0
`define WR_TRANSMISSION_CFG_OR_TX_ETHTYPE 32'h00000001
`define WR_TRANSMISSION_CFG_OR_TX_MAC_LOC_OFFSET 1
`define WR_TRANSMISSION_CFG_OR_TX_MAC_LOC 32'h00000002
`define WR_TRANSMISSION_CFG_OR_TX_MAC_TAR_OFFSET 2
`define WR_TRANSMISSION_CFG_OR_TX_MAC_TAR 32'h00000004
`define WR_TRANSMISSION_CFG_OR_RX_ETHERTYPE_OFFSET 16
`define WR_TRANSMISSION_CFG_OR_RX_ETHERTYPE 32'h00010000
`define WR_TRANSMISSION_CFG_OR_RX_MAC_LOC_OFFSET 17
`define WR_TRANSMISSION_CFG_OR_RX_MAC_LOC 32'h00020000
`define WR_TRANSMISSION_CFG_OR_RX_MAC_REM_OFFSET 18
`define WR_TRANSMISSION_CFG_OR_RX_MAC_REM 32'h00040000
`define WR_TRANSMISSION_CFG_OR_RX_ACC_BROADCAST_OFFSET 19
`define WR_TRANSMISSION_CFG_OR_RX_ACC_BROADCAST 32'h00080000
`define WR_TRANSMISSION_CFG_OR_RX_FTR_REMOTE_OFFSET 20
`define WR_TRANSMISSION_CFG_OR_RX_FTR_REMOTE 32'h00100000
`define WR_TRANSMISSION_CFG_OR_RX_FIX_LAT_OFFSET 21
`define WR_TRANSMISSION_CFG_OR_RX_FIX_LAT 32'h00200000
`define ADDR_WR_TRANSMISSION_DBG_CTRL 7'h5c
`define WR_TRANSMISSION_DBG_CTRL_MUX_OFFSET 0
`define WR_TRANSMISSION_DBG_CTRL_MUX 32'h00000001
`define WR_TRANSMISSION_DBG_CTRL_START_BYTE_OFFSET 8
`define WR_TRANSMISSION_DBG_CTRL_START_BYTE 32'h0000ff00
`define ADDR_WR_TRANSMISSION_DBG_DATA 7'h60
`define ADDR_WR_TRANSMISSION_DBG_RX_BVALUE 7'h64
`define ADDR_WR_TRANSMISSION_DBG_TX_BVALUE 7'h68
`define ADDR_WR_TRANSMISSION_DUMMY 7'h6c
`define WR_TRANSMISSION_DUMMY_DUMMY_OFFSET 0
`define WR_TRANSMISSION_DUMMY_DUMMY 32'hffffffff
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