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White Rabbit core collection
Commit cb23c3c9 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_endpoint: ep_wishbone_controller: removed DMCR/DMSR registers (now DMTD is in the SoftPLL)

parent 29f7ca73
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modules/wr_endpoint/ep_wishbone_controller.vhd
View file @ cb23c3c9
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Sun Sep 11 14:48:01 2011
-- Created : Tue Oct 18 16:46:38 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -81,8 +81,6 @@ signal ep_fcr_tx_thr_int : std_logic_vector(7 downto 0);
signal ep_fcr_tx_quanta_int : std_logic_vector(15 downto 0);
signal ep_mach_int : std_logic_vector(15 downto 0);
signal ep_macl_int : std_logic_vector(31 downto 0);
signal ep_dmcr_en_int : std_logic ;
signal ep_dmcr_n_avg_int : std_logic_vector(11 downto 0);
signal ep_mdio_cr_addr_int : std_logic_vector(7 downto 0);
signal ep_mdio_cr_rw_int : std_logic ;
signal ep_mdio_asr_phyad_int : std_logic_vector(7 downto 0);
......@@ -150,9 +148,6 @@ begin
ep_fcr_tx_quanta_int <= "0000000000000000";
ep_mach_int <= "0000000000000000";
ep_macl_int <= "00000000000000000000000000000000";
ep_dmcr_en_int <= '0';
ep_dmcr_n_avg_int <= "000000000000";
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.mdio_cr_data_wr_o <= '0';
ep_mdio_cr_addr_int <= "00000000";
ep_mdio_cr_rw_int <= '0';
......@@ -170,7 +165,6 @@ begin
regs_o.pfcr0_mm_addr_wr_o <= '0';
regs_o.pfcr0_mm_write_wr_o <= '0';
regs_o.pfcr0_mm_data_msb_wr_o <= '0';
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.mdio_cr_data_wr_o <= '0';
regs_o.dsr_lact_load_o <= '0';
ack_in_progress <= '0';
......@@ -182,7 +176,6 @@ begin
regs_o.pfcr0_mm_addr_wr_o <= '0';
regs_o.pfcr0_mm_write_wr_o <= '0';
regs_o.pfcr0_mm_data_msb_wr_o <= '0';
regs_o.dmsr_ps_rdy_load_o <= '0';
regs_o.mdio_cr_data_wr_o <= '0';
regs_o.dsr_lact_load_o <= '0';
end if;
......@@ -190,8 +183,8 @@ begin
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(5) is
when '0' =>
case rwaddr_reg(4 downto 0) is
when "00000" =>
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
ep_ecr_portid_int <= wrdata_reg(4 downto 0);
ep_ecr_rst_cnt_int <= wrdata_reg(5);
......@@ -234,7 +227,7 @@ begin
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00001" =>
when "0001" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ep_tscr_en_txts_int <= wrdata_reg(0);
......@@ -278,7 +271,7 @@ begin
end if;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "00010" =>
when "0010" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ep_rfcr_a_runt_int <= wrdata_reg(0);
......@@ -306,7 +299,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
when "0011" =>
if (wb_we_i = '1') then
ep_vcr0_qmode_int <= wrdata_reg(1 downto 0);
rddata_reg(2) <= 'X';
......@@ -335,7 +328,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
when "0100" =>
if (wb_we_i = '1') then
regs_o.vcr1_vid_wr_o <= '1';
regs_o.vcr1_value_wr_o <= '1';
......@@ -375,7 +368,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
when "0101" =>
if (wb_we_i = '1') then
regs_o.pfcr0_mm_addr_wr_o <= '1';
regs_o.pfcr0_mm_write_wr_o <= '1';
......@@ -418,7 +411,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
when "0110" =>
if (wb_we_i = '1') then
ep_pfcr1_mm_data_lsb_int <= wrdata_reg(11 downto 0);
else
......@@ -446,7 +439,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
when "0111" =>
if (wb_we_i = '1') then
ep_tcar_pcp_map_int <= wrdata_reg(23 downto 0);
else
......@@ -462,7 +455,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
when "1000" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ep_fcr_rxpause_int <= wrdata_reg(0);
......@@ -484,7 +477,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
when "1001" =>
if (wb_we_i = '1') then
ep_mach_int <= wrdata_reg(15 downto 0);
else
......@@ -508,7 +501,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
when "1010" =>
if (wb_we_i = '1') then
ep_macl_int <= wrdata_reg(31 downto 0);
else
......@@ -516,54 +509,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
ep_dmcr_en_int <= wrdata_reg(0);
ep_dmcr_n_avg_int <= wrdata_reg(27 downto 16);
else
rddata_reg(0) <= ep_dmcr_en_int;
rddata_reg(27 downto 16) <= ep_dmcr_n_avg_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
rddata_reg(24) <= 'X';
regs_o.dmsr_ps_rdy_load_o <= '1';
else
rddata_reg(23 downto 0) <= regs_i.dmsr_ps_val_i;
rddata_reg(24) <= regs_i.dmsr_ps_rdy_i;
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
when "1011" =>
if (wb_we_i = '1') then
regs_o.mdio_cr_data_wr_o <= '1';
ep_mdio_cr_addr_int <= wrdata_reg(23 downto 16);
......@@ -598,7 +544,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
when "1100" =>
if (wb_we_i = '1') then
ep_mdio_asr_phyad_int <= wrdata_reg(23 downto 16);
rddata_reg(31) <= 'X';
......@@ -616,14 +562,14 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
when "1101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= "11001010111111101011101010111110";
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
when "1110" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
......@@ -823,13 +769,6 @@ begin
regs_o.mach_o <= ep_mach_int;
-- MAC Address
regs_o.macl_o <= ep_macl_int;
-- DMTD Phase measurement enable
regs_o.dmcr_en_o <= ep_dmcr_en_int;
-- DMTD averaging samples
regs_o.dmcr_n_avg_o <= ep_dmcr_n_avg_int;
-- DMTD Phase shift value
-- DMTD Phase shift value ready
regs_o.dmsr_ps_rdy_o <= wrdata_reg(24);
-- MDIO Register Value
-- pass-through field: MDIO Register Value in register: MDIO Control Register
regs_o.mdio_cr_data_o <= wrdata_reg(15 downto 0);
......
modules/wr_endpoint/ep_wishbone_controller.wb
View file @ cb23c3c9
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : Wishbone Register Block (slave)
-- Project : White Rabbit MAC/Endpoint
-------------------------------------------------------------------------------
-- File : ep_wishbone_controller.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-18
-------------------------------------------------------------------------------
-- Description: Description of all non-PCS endpoint control registers
-- for wbgen2 Wishbone slave core generator.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1l.html
--
-------------------------------------------------------------------------------
peripheral {
name = "WR switch endpoint controller";
......@@ -445,55 +479,6 @@ peripheral {
};
};
reg {
name = "DMTD Control Register";
prefix = "DMCR";
field {
name = "DMTD Phase measurement enable";
description = "1: enables DMTD phase measurement";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
description = "Number of raw DMTD phase samples averaged in every measurement cycle";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "DMTD Status register";
prefix = "DMSR";
field {
name = "DMTD Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "DMTD Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
reg {
name = "MDIO Control Register";
description = "Register controlling the read/write operations on the MDIO PHY/PCS interface. Writing to this register clears the READY bit in the MDIO Status Register";
......
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