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White Rabbit core collection
Commit cc39f753 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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[spi-flash]: few missing bits and pieces to the last commit

parent 6e339ab1
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Showing with 49 additions and 47 deletions
modules/wrc_core/wr_core.vhd
View file @ cc39f753
......@@ -167,7 +167,7 @@ entity wr_core is
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
......@@ -762,7 +762,7 @@ begin
btn1_i => btn1_i,
btn2_i => btn2_i,
spi_sclk_o => spi_sclk_o,
spi_cs_o => spi_cs_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
......
modules/wrc_core/wrc_periph.vhd
View file @ cc39f753
......@@ -61,6 +61,7 @@ entity wrc_periph is
btn1_i : in std_logic;
btn2_i : in std_logic;
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
......@@ -249,6 +250,7 @@ begin
if rst_n_i = '0' then
spi_sclk_o <= '0';
spi_mosi_o <= '0';
spi_ncs_o <= '1';
else
if(sysc_regs_o.gpsr_spi_sclk_load_o = '1' and sysc_regs_o.gpsr_spi_sclk_o = '1') then
spi_sclk_o <= '1';
......@@ -256,10 +258,10 @@ begin
spi_sclk_o <= '0';
end if;
if(sysc_regs_o.gpsr_spi_cs_load_o = '1' and sysc_regs_o.gpsr_spi_cs_o = '1') then
spi_sclk_o <= '1';
if(sysc_regs_o.gpsr_spi_ncs_load_o = '1' and sysc_regs_o.gpsr_spi_ncs_o = '1') then
spi_ncs_o <= '1';
elsif(sysc_regs_o.gpcr_spi_cs_o = '1') then
spi_sclk_o <= '0';
spi_ncs_o <= '0';
end if;
if(sysc_regs_o.gpsr_spi_mosi_load_o = '1' and sysc_regs_o.gpsr_spi_mosi_o = '1') then
......@@ -270,7 +272,7 @@ begin
end if;
end process;
sysc_regs_i.gpsr_spi_sclk_i <= '0';
sysc_regs_i.gpsr_spi_cs_i <= '0';
sysc_regs_i.gpsr_spi_ncs_i <= '0';
sysc_regs_i.gpsr_spi_mosi_i <= '0';
sysc_regs_i.gpsr_spi_miso_i <= spi_miso_i;
......
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ cc39f753
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Sep 25 13:27:18 2013
-- Created : Wed Sep 25 14:35:39 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -28,7 +28,7 @@ package sysc_wbgen2_pkg is
gpsr_sfp_scl_i : std_logic;
gpsr_sfp_sda_i : std_logic;
gpsr_spi_sclk_i : std_logic;
gpsr_spi_cs_i : std_logic;
gpsr_spi_ncs_i : std_logic;
gpsr_spi_mosi_i : std_logic;
gpsr_spi_miso_i : std_logic;
hwfr_memsize_i : std_logic_vector(3 downto 0);
......@@ -45,7 +45,7 @@ package sysc_wbgen2_pkg is
gpsr_sfp_scl_i => '0',
gpsr_sfp_sda_i => '0',
gpsr_spi_sclk_i => '0',
gpsr_spi_cs_i => '0',
gpsr_spi_ncs_i => '0',
gpsr_spi_mosi_i => '0',
gpsr_spi_miso_i => '0',
hwfr_memsize_i => (others => '0'),
......@@ -72,8 +72,8 @@ package sysc_wbgen2_pkg is
gpsr_sfp_sda_load_o : std_logic;
gpsr_spi_sclk_o : std_logic;
gpsr_spi_sclk_load_o : std_logic;
gpsr_spi_cs_o : std_logic;
gpsr_spi_cs_load_o : std_logic;
gpsr_spi_ncs_o : std_logic;
gpsr_spi_ncs_load_o : std_logic;
gpsr_spi_mosi_o : std_logic;
gpsr_spi_mosi_load_o : std_logic;
gpcr_led_stat_o : std_logic;
......@@ -105,8 +105,8 @@ package sysc_wbgen2_pkg is
gpsr_sfp_sda_load_o => '0',
gpsr_spi_sclk_o => '0',
gpsr_spi_sclk_load_o => '0',
gpsr_spi_cs_o => '0',
gpsr_spi_cs_load_o => '0',
gpsr_spi_ncs_o => '0',
gpsr_spi_ncs_load_o => '0',
gpsr_spi_mosi_o => '0',
gpsr_spi_mosi_load_o => '0',
gpcr_led_stat_o => '0',
......@@ -157,7 +157,7 @@ tmp.gpsr_sfp_det_i := f_x_to_zero(left.gpsr_sfp_det_i) or f_x_to_zero(right.gpsr
tmp.gpsr_sfp_scl_i := f_x_to_zero(left.gpsr_sfp_scl_i) or f_x_to_zero(right.gpsr_sfp_scl_i);
tmp.gpsr_sfp_sda_i := f_x_to_zero(left.gpsr_sfp_sda_i) or f_x_to_zero(right.gpsr_sfp_sda_i);
tmp.gpsr_spi_sclk_i := f_x_to_zero(left.gpsr_spi_sclk_i) or f_x_to_zero(right.gpsr_spi_sclk_i);
tmp.gpsr_spi_cs_i := f_x_to_zero(left.gpsr_spi_cs_i) or f_x_to_zero(right.gpsr_spi_cs_i);
tmp.gpsr_spi_ncs_i := f_x_to_zero(left.gpsr_spi_ncs_i) or f_x_to_zero(right.gpsr_spi_ncs_i);
tmp.gpsr_spi_mosi_i := f_x_to_zero(left.gpsr_spi_mosi_i) or f_x_to_zero(right.gpsr_spi_mosi_i);
tmp.gpsr_spi_miso_i := f_x_to_zero(left.gpsr_spi_miso_i) or f_x_to_zero(right.gpsr_spi_miso_i);
tmp.hwfr_memsize_i := f_x_to_zero(left.hwfr_memsize_i) or f_x_to_zero(right.hwfr_memsize_i);
......
modules/wrc_core/wrc_syscon_regs.h
View file @ cc39f753
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Wed Sep 25 13:27:18 2013
* Created : Wed Sep 25 14:35:39 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -77,8 +77,8 @@
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
/* definitions for field: SPI bitbanged CS in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_CS WBGEN2_GEN_MASK(11, 1)
/* definitions for field: SPI bitbanged NCS in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_NCS WBGEN2_GEN_MASK(11, 1)
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
......
modules/wrc_core/wrc_syscon_wb.vhd
View file @ cc39f753
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Wed Sep 25 13:27:18 2013
-- Created : Wed Sep 25 14:35:39 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -100,7 +100,7 @@ begin
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
regs_o.gpsr_spi_sclk_load_o <= '0';
regs_o.gpsr_spi_cs_load_o <= '0';
regs_o.gpsr_spi_ncs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
......@@ -127,7 +127,7 @@ begin
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
regs_o.gpsr_spi_sclk_load_o <= '0';
regs_o.gpsr_spi_cs_load_o <= '0';
regs_o.gpsr_spi_ncs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
......@@ -146,7 +146,7 @@ begin
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
regs_o.gpsr_spi_sclk_load_o <= '0';
regs_o.gpsr_spi_cs_load_o <= '0';
regs_o.gpsr_spi_ncs_load_o <= '0';
regs_o.gpsr_spi_mosi_load_o <= '0';
end if;
else
......@@ -201,21 +201,21 @@ begin
regs_o.gpsr_sfp_scl_load_o <= '1';
regs_o.gpsr_sfp_sda_load_o <= '1';
regs_o.gpsr_spi_sclk_load_o <= '1';
regs_o.gpsr_spi_cs_load_o <= '1';
regs_o.gpsr_spi_ncs_load_o <= '1';
regs_o.gpsr_spi_mosi_load_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= regs_i.gpsr_fmc_scl_i;
rddata_reg(3) <= regs_i.gpsr_fmc_sda_i;
rddata_reg(4) <= 'X';
rddata_reg(4) <= '0';
rddata_reg(5) <= regs_i.gpsr_btn1_i;
rddata_reg(6) <= regs_i.gpsr_btn2_i;
rddata_reg(7) <= regs_i.gpsr_sfp_det_i;
rddata_reg(8) <= regs_i.gpsr_sfp_scl_i;
rddata_reg(9) <= regs_i.gpsr_sfp_sda_i;
rddata_reg(10) <= regs_i.gpsr_spi_sclk_i;
rddata_reg(11) <= regs_i.gpsr_spi_cs_i;
rddata_reg(11) <= regs_i.gpsr_spi_ncs_i;
rddata_reg(12) <= regs_i.gpsr_spi_mosi_i;
rddata_reg(13) <= regs_i.gpsr_spi_miso_i;
rddata_reg(14) <= 'X';
......@@ -250,15 +250,15 @@ begin
sysc_gpcr_spi_cs_int <= wrdata_reg(11);
sysc_gpcr_spi_mosi_int <= wrdata_reg(12);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(3) <= '0';
rddata_reg(8) <= '0';
rddata_reg(9) <= '0';
rddata_reg(10) <= '0';
rddata_reg(11) <= '0';
rddata_reg(12) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -430,8 +430,8 @@ begin
regs_o.gpsr_sfp_sda_o <= wrdata_reg(9);
-- SPI bitbanged SCLK
regs_o.gpsr_spi_sclk_o <= wrdata_reg(10);
-- SPI bitbanged CS
regs_o.gpsr_spi_cs_o <= wrdata_reg(11);
-- SPI bitbanged NCS
regs_o.gpsr_spi_ncs_o <= wrdata_reg(11);
-- SPI bitbanged MOSI
regs_o.gpsr_spi_mosi_o <= wrdata_reg(12);
-- SPI bitbanged MISO
......
modules/wrc_core/wrc_syscon_wb.wb
View file @ cc39f753
......@@ -141,9 +141,9 @@ peripheral {
};
field {
name = "SPI bitbanged CS";
prefix = "spi_cs";
description = "write 1: drive SPI CS to 1\
name = "SPI bitbanged NCS";
prefix = "spi_ncs";
description = "write 1: drive SPI NCS to 1\
read: always 0";
type = BIT;
access_bus = READ_WRITE;
......
modules/wrc_core/wrcore_pkg.vhd
View file @ cc39f753
......@@ -216,7 +216,7 @@ package wrcore_pkg is
btn1_i : in std_logic;
btn2_i : in std_logic;
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(0 to 2);
......@@ -350,7 +350,7 @@ package wrcore_pkg is
btn1_i : in std_logic := 'H';
btn2_i : in std_logic := 'H';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
......@@ -482,7 +482,7 @@ package wrcore_pkg is
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
......
modules/wrc_core/xwr_core.vhd
View file @ cc39f753
......@@ -151,7 +151,7 @@ entity xwr_core is
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
......@@ -278,7 +278,7 @@ begin
btn1_i => btn1_i,
btn2_i => btn2_i,
spi_sclk_o => spi_sclk_o,
spi_cs_o => spi_cs_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ cc39f753
......@@ -88,7 +88,7 @@ entity spec_top is
button2_i : in std_logic := 'H';
spi_sclk_o : out std_logic;
spi_cs_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := 'L';
......@@ -705,7 +705,7 @@ begin
btn1_i => button1_i,
btn2_i => button2_i,
spi_sclk_o => spi_sclk_o,
spi_cs_o => spi_cs_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
......
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