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White Rabbit core collection
Commit dc68dadc authored by Peter Jansweijer's avatar Peter Jansweijer
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gthe4, set TXOUTCLK 125 MHz

parent 7621f92c
Pipeline #4700 failed with stage
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    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2.v
    View file @ dc68dadc
    ......@@ -56,8 +56,8 @@
    1,C_CPLL_VCO_FREQUENCY=2500.0,C_FORCE_COMMONS=0,C_FREERUN_FREQUENCY=62.5,C_GT_TYPE=2,C_GT_REV=57,C_INCLUDE_CPLL_CAL=2,C_ENABLE_COMMON_USRCLK=0,C_USER_GTPOWERGOOD_DELAY_EN=1,C_SIM_CPLL_CAL_BYPASS=1,C_LOCATE_COMMON=0,C_LOCATE_RESET_CONTROLLER=0,C_LOCATE_USER_DATA_WIDTH_SIZING=0,C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_IN_SYSTEM_IBERT_CORE=1,C_LOCATE_RX_USER_CLOCKING=0,C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER=0,C_LOCATE_TX_USER_CLOCKING=0,C_RESET_CONTROLLER_INSTANCE_CTRL=0,C_RX_BUFFBYPASS_MODE=0\
    ,C_RX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_RX_BUFFER_MODE=0,C_RX_CB_DISP=00000000,C_RX_CB_K=00000000,C_RX_CB_MAX_LEVEL=1,C_RX_CB_LEN_SEQ=1,C_RX_CB_NUM_SEQ=0,C_RX_CB_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_CC_DISP=00000000,C_RX_CC_ENABLE=0,C_RESET_SEQUENCE_INTERVAL=0,C_RX_CC_K=00000000,C_RX_CC_LEN_SEQ=1,C_RX_CC_NUM_SEQ=0,C_RX_CC_PERIODICITY=5000,C_RX_CC_VAL=00000000000000000000000000000000000000000000000000000000000000000000000000000000,C_RX_COMMA_M_EN\
    ABLE=0,C_RX_COMMA_M_VAL=1010000011,C_RX_COMMA_P_ENABLE=0,C_RX_COMMA_P_VAL=0101111100,C_RX_DATA_DECODING=0,C_RX_ENABLE=1,C_RX_INT_DATA_WIDTH=20,C_RX_LINE_RATE=1.25,C_RX_MASTER_CHANNEL_IDX=0,C_RX_OUTCLK_BUFG_GT_DIV=1,C_RX_OUTCLK_FREQUENCY=62.5000000,C_RX_OUTCLK_SOURCE=1,C_RX_PLL_TYPE=2,C_RX_RECCLK_OUTPUT=0x000000000000000000000000000000000000000000000000,C_RX_REFCLK_FREQUENCY=100,C_RX_SLIDE_MODE=1,C_RX_USER_CLOCKING_CONTENTS=0,C_RX_USER_CLOCKING_INSTANCE_CTRL=0,C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCL\
    K=1,C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_SOURCE=0,C_RX_USER_DATA_WIDTH=20,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=0,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=62.5,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=0,C_TX_ENABLE=1\
    ,C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX=0,C_TX_OUTCLK_BUFG_GT_DIV=1,C_TX_OUTCLK_FREQUENCY=62.5000000,C_TX_OUTCLK_SOURCE=4,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=100,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=1,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=20,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
    K=1,C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_RX_USER_CLOCKING_SOURCE=0,C_RX_USER_DATA_WIDTH=20,C_RX_USRCLK_FREQUENCY=62.5000000,C_RX_USRCLK2_FREQUENCY=62.5000000,C_SECONDARY_QPLL_ENABLE=0,C_SECONDARY_QPLL_REFCLK_FREQUENCY=257.8125,C_TOTAL_NUM_CHANNELS=1,C_TOTAL_NUM_COMMONS=0,C_TOTAL_NUM_COMMONS_EXAMPLE=0,C_TXPROGDIV_FREQ_ENABLE=1,C_TXPROGDIV_FREQ_SOURCE=2,C_TXPROGDIV_FREQ_VAL=125,C_TX_BUFFBYPASS_MODE=0,C_TX_BUFFER_BYPASS_INSTANCE_CTRL=0,C_TX_BUFFER_MODE=0,C_TX_DATA_ENCODING=0,C_TX_ENABLE=1,\
    C_TX_INT_DATA_WIDTH=20,C_TX_LINE_RATE=1.25,C_TX_MASTER_CHANNEL_IDX=0,C_TX_OUTCLK_BUFG_GT_DIV=2,C_TX_OUTCLK_FREQUENCY=62.5000000,C_TX_OUTCLK_SOURCE=4,C_TX_PLL_TYPE=2,C_TX_REFCLK_FREQUENCY=100,C_TX_USER_CLOCKING_CONTENTS=0,C_TX_USER_CLOCKING_INSTANCE_CTRL=0,C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK=1,C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2=1,C_TX_USER_CLOCKING_SOURCE=0,C_TX_USER_DATA_WIDTH=20,C_TX_USRCLK_FREQUENCY=62.5000000,C_TX_USRCLK2_FREQUENCY=62.5000000}" *)
    (* DowngradeIPIdentifiedWarnings = "yes" *)
    module gtwizard_ultrascale_2 (
    gtwiz_userclk_tx_reset_in,
    ......@@ -244,9 +244,9 @@ output wire [0 : 0] txresetdone_out;
    .C_TOTAL_NUM_CHANNELS(1),
    .C_TOTAL_NUM_COMMONS(0),
    .C_TOTAL_NUM_COMMONS_EXAMPLE(0),
    .C_TXPROGDIV_FREQ_ENABLE(0),
    .C_TXPROGDIV_FREQ_ENABLE(1),
    .C_TXPROGDIV_FREQ_SOURCE(2),
    .C_TXPROGDIV_FREQ_VAL(62.5),
    .C_TXPROGDIV_FREQ_VAL(125),
    .C_TX_BUFFBYPASS_MODE(0),
    .C_TX_BUFFER_BYPASS_INSTANCE_CTRL(0),
    .C_TX_BUFFER_MODE(0),
    ......@@ -255,7 +255,7 @@ output wire [0 : 0] txresetdone_out;
    .C_TX_INT_DATA_WIDTH(20),
    .C_TX_LINE_RATE(1.25),
    .C_TX_MASTER_CHANNEL_IDX(0),
    .C_TX_OUTCLK_BUFG_GT_DIV(1),
    .C_TX_OUTCLK_BUFG_GT_DIV(2),
    .C_TX_OUTCLK_FREQUENCY(62.5000000),
    .C_TX_OUTCLK_SOURCE(4),
    .C_TX_PLL_TYPE(2),
    ......
    platform/xilinx/wr_gtp_phy/xilinx-ip/gthe4_lp/gtwizard_ultrascale_2_gthe4_channel_wrapper.v
    View file @ dc68dadc
    ......@@ -1339,8 +1339,8 @@ gtwizard_ultrascale_v1_7_13_gthe4_channel #(
    .GTHE4_CHANNEL_TX_PMA_POWER_SAVE (1'b0),
    .GTHE4_CHANNEL_TX_PMA_RSV0 (16'b0000000000001000),
    .GTHE4_CHANNEL_TX_PREDRV_CTRL (2),
    .GTHE4_CHANNEL_TX_PROGCLK_SEL ("PREPI"),
    .GTHE4_CHANNEL_TX_PROGDIV_CFG (40.0),
    .GTHE4_CHANNEL_TX_PROGCLK_SEL ("CPLL"),
    .GTHE4_CHANNEL_TX_PROGDIV_CFG (20.0),
    .GTHE4_CHANNEL_TX_PROGDIV_RATE (16'b0000000000000001),
    .GTHE4_CHANNEL_TX_QPI_STATUS_EN (1'b0),
    .GTHE4_CHANNEL_TX_RXDETECT_CFG (14'b00000000110010),
    ......
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