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White Rabbit core collection
Commit e44976ee authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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make rx ts trigger delay configurable

parent ebc5758d
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Showing with 395 additions and 20 deletions
modules/wr_endpoint/Manifest.py
View file @ e44976ee
......@@ -30,6 +30,7 @@ files = [ "endpoint_private_pkg.vhd",
"ep_wishbone_controller.vhd",
"ep_registers_pkg.vhd",
"ep_crc32_pkg.vhd",
"trig_delay.vhd",
"endpoint_pkg.vhd",
"wr_endpoint.vhd",
"xwr_endpoint.vhd"
......
modules/wr_endpoint/endpoint_pkg.vhd
View file @ e44976ee
......@@ -106,7 +106,10 @@ package endpoint_pkg is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
led_link_o : out std_logic;
led_act_o : out std_logic);
led_act_o : out std_logic;
debug_sr_rst_i : in std_logic;
debug_sr_d_i : in std_logic;
debug_sr_en_i : in std_logic);
end component;
constant c_xwr_endpoint_sdb : t_sdb_device := (
......@@ -191,7 +194,10 @@ package endpoint_pkg is
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
led_link_o : out std_logic;
led_act_o : out std_logic);
led_act_o : out std_logic;
debug_sr_rst_i : in std_logic;
debug_sr_d_i : in std_logic;
debug_sr_en_i : in std_logic);
end component;
end endpoint_pkg;
......
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @ e44976ee
......@@ -107,7 +107,12 @@ entity ep_timestamping_unit is
-------------------------------------------------------------------------------
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers
regs_o : out t_ep_in_registers;
debug_sr_rst_i : in std_logic;
debug_sr_d_i : in std_logic;
debug_sr_en_i : in std_logic
);
end ep_timestamping_unit;
......@@ -164,6 +169,22 @@ architecture syn of ep_timestamping_unit is
signal cal_count : unsigned(5 downto 0);
signal rx_trigger_mask, rx_trigger_a, rx_cal_pulse_a : std_logic;
-- TEMP
component trig_delay
generic (
g_length : integer := 64);
port (
d_i : in std_logic;
q_o : out std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
sr_rst_i : in std_logic;
sr_d_i : in std_logic;
sr_en_i : in std_logic);
end component;
signal rx_trigger_delayed : std_logic;
begin -- syn
......@@ -225,6 +246,18 @@ begin -- syn
rx_trigger_a <= (rx_timestamp_trigger_p_a_i and rx_trigger_mask) or rx_cal_pulse_a;
U_TDEL: trig_delay
port map(
d_i => rx_trigger_a,
q_o => rx_trigger_delayed,
clk_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
sr_rst_i => debug_sr_rst_i,
sr_d_i => debug_sr_d_i,
sr_en_i => debug_sr_en_i);
-- Sync chains for timestamp strobes: 4 combinations - (TX-RX) -> (rising/falling)
sync_ffs_tx_r : gc_sync_ffs
generic map (
......@@ -245,7 +278,7 @@ begin -- syn
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
data_i => rx_trigger_a,
data_i => rx_trigger_delayed,
synced_o => open,
npulse_o => open,
ppulse_o => take_rx_synced_p);
......@@ -268,7 +301,7 @@ begin -- syn
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_ref_i,
data_i => rx_trigger_a,
data_i => rx_trigger_delayed,
synced_o => open,
npulse_o => open,
ppulse_o => take_rx_synced_p_fedge);
......
modules/wr_endpoint/trig_delay.vhd 0 → 100644
View file @ e44976ee
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity trig_delay is
generic (
g_length : integer := 64);
port (
d_i : in std_logic;
q_o : out std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
sr_rst_i : in std_logic;
sr_d_i : in std_logic;
sr_en_i : in std_logic
);
end trig_delay;
architecture rtl of trig_delay is
component LUT6
generic (
INIT : bit_vector);
port (
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic);
end component;
signal dly, dly_d : std_logic_vector(g_length downto 0);
signal sel_reg : std_logic_vector(g_length-1 downto 0);
signal en_d0 : std_logic;
begin -- rtl
gen_dl : for i in 0 to g_length-1 generate
LUT6_1 : LUT6
generic map (
INIT => x"00000000000000d8")
port map (
O => dly(i+1),
I0 => sel_reg(i),
I1 => dly(i),
I2 => d_i,
I3 => '0',
I4 => '0',
I5 => '0');
-- dly(i+1) <= transport dly_d(i+1) after 100ps;
end generate gen_dl;
dly(0) <= d_i;
q_o <= dly(g_length);
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' or sr_rst_i = '1' then
sel_reg <= (others => '0');
en_d0 <= '0';
else
if(sr_en_i = '1' and en_d0 = '0') then
sel_reg <= sel_reg(sel_reg'length-2 downto 0) & sr_d_i;
end if;
en_d0 <= sr_en_i;
end if;
end if;
end process;
end rtl;
modules/wr_endpoint/wr_endpoint.vhd
View file @ e44976ee
......@@ -215,7 +215,11 @@ entity wr_endpoint is
-------------------------------------------------------------------------------
led_link_o : out std_logic;
led_act_o : out std_logic
led_act_o : out std_logic;
debug_sr_rst_i : in std_logic;
debug_sr_d_i : in std_logic;
debug_sr_en_i : in std_logic
);
......@@ -378,7 +382,11 @@ architecture syn of wr_endpoint is
txts_timestamp_stb_o : out std_logic;
txts_timestamp_valid_o : out std_logic;
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers);
regs_o : out t_ep_in_registers;
debug_sr_rst_i : in std_logic;
debug_sr_d_i : in std_logic;
debug_sr_en_i : in std_logic);
end component;
-------------------------------------------------------------------------------
......@@ -774,7 +782,13 @@ begin
txts_timestamp_valid_o => txts_timestamp_valid,
regs_i => regs_fromwb,
regs_o => regs_towb_tsu);
regs_o => regs_towb_tsu,
debug_sr_rst_i => debug_sr_rst_i,
debug_sr_d_i => debug_sr_d_i,
debug_sr_en_i => debug_sr_en_i
);
-------------------------------------------------------------------------------
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ e44976ee
......@@ -178,8 +178,11 @@ entity xwr_endpoint is
-------------------------------------------------------------------------------
led_link_o : out std_logic;
led_act_o : out std_logic
led_act_o : out std_logic;
debug_sr_rst_i : in std_logic;
debug_sr_d_i : in std_logic;
debug_sr_en_i : in std_logic
);
end xwr_endpoint;
......@@ -278,7 +281,11 @@ begin
wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall,
led_link_o => led_link_o,
led_act_o => led_act_o);
led_act_o => led_act_o,
debug_sr_rst_i => debug_sr_rst_i,
debug_sr_d_i => debug_sr_d_i,
debug_sr_en_i => debug_sr_en_i
);
wb_o.err <= '0';
wb_o.rty <= '0';
......
modules/wrc_core/wr_core.vhd
View file @ e44976ee
......@@ -457,6 +457,11 @@ architecture struct of wr_core is
--signal TRIG1 : std_logic_vector(31 downto 0);
--signal TRIG2 : std_logic_vector(31 downto 0);
--signal TRIG3 : std_logic_vector(31 downto 0);
--TEMP
signal debug_sr_rst : std_logic;
signal debug_sr_d : std_logic;
signal debug_sr_en : std_logic;
begin
rst_aux_n_o <= rst_net_n;
......@@ -627,7 +632,10 @@ begin
wb_i => ep_wb_in,
wb_o => ep_wb_out,
led_link_o => ep_led_link,
led_act_o => led_act_o);
led_act_o => led_act_o,
debug_sr_rst_i => debug_sr_rst,
debug_sr_d_i => debug_sr_d,
debug_sr_en_i => debug_sr_en);
ep_txtsu_ack <= txtsu_ack_i or mnic_txtsu_ack;
led_link_o <= ep_led_link;
......@@ -755,7 +763,11 @@ begin
owr_pwren_o => owr_pwren_o,
owr_en_o => owr_en_o,
owr_i => owr_i
owr_i => owr_i,
debug_sr_rst_o => debug_sr_rst,
debug_sr_d_o => debug_sr_d,
debug_sr_en_o => debug_sr_en
);
U_Adapter : wb_slave_adapter
......
modules/wrc_core/wrc_periph.vhd
View file @ e44976ee
......@@ -69,7 +69,11 @@ entity wrc_periph is
-- 1-Wire
owr_pwren_o: out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0)
owr_i : in std_logic_vector(1 downto 0);
debug_sr_rst_o : out std_logic;
debug_sr_d_o : out std_logic;
debug_sr_en_o : out std_logic
);
end wrc_periph;
......@@ -133,6 +137,32 @@ begin
end if;
end process;
----------------------
-- DEBUG
----------------------
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(sysc_regs_o.gpsr_dbg_rst_o = '1') then
debug_sr_rst_o <= '1';
elsif(sysc_regs_o.gpcr_dbg_rst_o = '1') then
debug_sr_rst_o <= '0';
end if;
if(sysc_regs_o.gpsr_dbg_d_o = '1') then
debug_sr_d_o <= '1';
elsif(sysc_regs_o.gpcr_dbg_d_o = '1') then
debug_sr_d_o <= '0';
end if;
if(sysc_regs_o.gpsr_dbg_en_o = '1') then
debug_sr_en_o <= '1';
elsif(sysc_regs_o.gpcr_dbg_en_o = '1') then
debug_sr_en_o <= '0';
end if;
end if;
end process;
-------------------------------------
-- buttons
-------------------------------------
......
modules/wrc_core/wrc_syscon_pkg.vhd
View file @ e44976ee
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Thu Feb 14 10:45:15 2013
-- Created : Tue Nov 12 11:10:02 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -62,12 +62,18 @@ package sysc_wbgen2_pkg is
gpsr_sfp_scl_load_o : std_logic;
gpsr_sfp_sda_o : std_logic;
gpsr_sfp_sda_load_o : std_logic;
gpsr_dbg_rst_o : std_logic;
gpsr_dbg_d_o : std_logic;
gpsr_dbg_en_o : std_logic;
gpcr_led_stat_o : std_logic;
gpcr_led_link_o : std_logic;
gpcr_fmc_scl_o : std_logic;
gpcr_fmc_sda_o : std_logic;
gpcr_sfp_scl_o : std_logic;
gpcr_sfp_sda_o : std_logic;
gpcr_dbg_rst_o : std_logic;
gpcr_dbg_d_o : std_logic;
gpcr_dbg_en_o : std_logic;
tcr_enable_o : std_logic;
end record;
......@@ -86,12 +92,18 @@ package sysc_wbgen2_pkg is
gpsr_sfp_scl_load_o => '0',
gpsr_sfp_sda_o => '0',
gpsr_sfp_sda_load_o => '0',
gpsr_dbg_rst_o => '0',
gpsr_dbg_d_o => '0',
gpsr_dbg_en_o => '0',
gpcr_led_stat_o => '0',
gpcr_led_link_o => '0',
gpcr_fmc_scl_o => '0',
gpcr_fmc_sda_o => '0',
gpcr_sfp_scl_o => '0',
gpcr_sfp_sda_o => '0',
gpcr_dbg_rst_o => '0',
gpcr_dbg_d_o => '0',
gpcr_dbg_en_o => '0',
tcr_enable_o => '0'
);
function "or" (left, right: t_sysc_in_registers) return t_sysc_in_registers;
......
modules/wrc_core/wrc_syscon_regs.h
View file @ e44976ee
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Thu Feb 14 10:45:15 2013
* Created : Tue Nov 12 11:10:02 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -74,6 +74,15 @@
/* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: DBG rst in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_DBG_RST WBGEN2_GEN_MASK(10, 1)
/* definitions for field: DBG D in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_DBG_D WBGEN2_GEN_MASK(11, 1)
/* definitions for field: DBG EN in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_DBG_EN WBGEN2_GEN_MASK(12, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
......@@ -94,6 +103,15 @@
/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: DBG rst in reg: GPIO Clear Register */
#define SYSC_GPCR_DBG_RST WBGEN2_GEN_MASK(10, 1)
/* definitions for field: DBG D in reg: GPIO Clear Register */
#define SYSC_GPCR_DBG_D WBGEN2_GEN_MASK(11, 1)
/* definitions for field: DBG EN in reg: GPIO Clear Register */
#define SYSC_GPCR_DBG_EN WBGEN2_GEN_MASK(12, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
......
modules/wrc_core/wrc_syscon_wb.vhd
View file @ e44976ee
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrc_syscon_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Thu Feb 14 10:45:15 2013
-- Created : Tue Nov 12 11:10:02 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -44,6 +44,12 @@ signal sysc_gpsr_led_link_dly0 : std_logic ;
signal sysc_gpsr_led_link_int : std_logic ;
signal sysc_gpsr_net_rst_dly0 : std_logic ;
signal sysc_gpsr_net_rst_int : std_logic ;
signal sysc_gpsr_dbg_rst_dly0 : std_logic ;
signal sysc_gpsr_dbg_rst_int : std_logic ;
signal sysc_gpsr_dbg_d_dly0 : std_logic ;
signal sysc_gpsr_dbg_d_int : std_logic ;
signal sysc_gpsr_dbg_en_dly0 : std_logic ;
signal sysc_gpsr_dbg_en_int : std_logic ;
signal sysc_gpcr_led_stat_dly0 : std_logic ;
signal sysc_gpcr_led_stat_int : std_logic ;
signal sysc_gpcr_led_link_dly0 : std_logic ;
......@@ -56,6 +62,12 @@ signal sysc_gpcr_sfp_scl_dly0 : std_logic ;
signal sysc_gpcr_sfp_scl_int : std_logic ;
signal sysc_gpcr_sfp_sda_dly0 : std_logic ;
signal sysc_gpcr_sfp_sda_int : std_logic ;
signal sysc_gpcr_dbg_rst_dly0 : std_logic ;
signal sysc_gpcr_dbg_rst_int : std_logic ;
signal sysc_gpcr_dbg_d_dly0 : std_logic ;
signal sysc_gpcr_dbg_d_int : std_logic ;
signal sysc_gpcr_dbg_en_dly0 : std_logic ;
signal sysc_gpcr_dbg_en_int : std_logic ;
signal sysc_tcr_enable_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
......@@ -93,12 +105,18 @@ begin
sysc_gpsr_net_rst_int <= '0';
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
sysc_gpsr_dbg_rst_int <= '0';
sysc_gpsr_dbg_d_int <= '0';
sysc_gpsr_dbg_en_int <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
sysc_gpcr_fmc_scl_int <= '0';
sysc_gpcr_fmc_sda_int <= '0';
sysc_gpcr_sfp_scl_int <= '0';
sysc_gpcr_sfp_sda_int <= '0';
sysc_gpcr_dbg_rst_int <= '0';
sysc_gpcr_dbg_d_int <= '0';
sysc_gpcr_dbg_en_int <= '0';
sysc_tcr_enable_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -114,12 +132,18 @@ begin
sysc_gpsr_net_rst_int <= '0';
regs_o.gpsr_sfp_scl_load_o <= '0';
regs_o.gpsr_sfp_sda_load_o <= '0';
sysc_gpsr_dbg_rst_int <= '0';
sysc_gpsr_dbg_d_int <= '0';
sysc_gpsr_dbg_en_int <= '0';
sysc_gpcr_led_stat_int <= '0';
sysc_gpcr_led_link_int <= '0';
sysc_gpcr_fmc_scl_int <= '0';
sysc_gpcr_fmc_sda_int <= '0';
sysc_gpcr_sfp_scl_int <= '0';
sysc_gpcr_sfp_sda_int <= '0';
sysc_gpcr_dbg_rst_int <= '0';
sysc_gpcr_dbg_d_int <= '0';
sysc_gpcr_dbg_en_int <= '0';
ack_in_progress <= '0';
else
regs_o.rstr_trig_wr_o <= '0';
......@@ -179,6 +203,9 @@ begin
sysc_gpsr_net_rst_int <= wrdata_reg(4);
regs_o.gpsr_sfp_scl_load_o <= '1';
regs_o.gpsr_sfp_sda_load_o <= '1';
sysc_gpsr_dbg_rst_int <= wrdata_reg(10);
sysc_gpsr_dbg_d_int <= wrdata_reg(11);
sysc_gpsr_dbg_en_int <= wrdata_reg(12);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
......@@ -190,9 +217,9 @@ begin
rddata_reg(7) <= regs_i.gpsr_sfp_det_i;
rddata_reg(8) <= regs_i.gpsr_sfp_scl_i;
rddata_reg(9) <= regs_i.gpsr_sfp_sda_i;
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(10) <= '0';
rddata_reg(11) <= '0';
rddata_reg(12) <= '0';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
......@@ -222,6 +249,9 @@ begin
sysc_gpcr_fmc_sda_int <= wrdata_reg(3);
sysc_gpcr_sfp_scl_int <= wrdata_reg(8);
sysc_gpcr_sfp_sda_int <= wrdata_reg(9);
sysc_gpcr_dbg_rst_int <= wrdata_reg(10);
sysc_gpcr_dbg_d_int <= wrdata_reg(11);
sysc_gpcr_dbg_en_int <= wrdata_reg(12);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
......@@ -229,6 +259,9 @@ begin
rddata_reg(3) <= '0';
rddata_reg(8) <= '0';
rddata_reg(9) <= '0';
rddata_reg(10) <= '0';
rddata_reg(11) <= '0';
rddata_reg(12) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -398,6 +431,45 @@ begin
regs_o.gpsr_sfp_scl_o <= wrdata_reg(8);
-- SFP I2C bitbanged SDA
regs_o.gpsr_sfp_sda_o <= wrdata_reg(9);
-- DBG rst
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpsr_dbg_rst_dly0 <= '0';
regs_o.gpsr_dbg_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpsr_dbg_rst_dly0 <= sysc_gpsr_dbg_rst_int;
regs_o.gpsr_dbg_rst_o <= sysc_gpsr_dbg_rst_int and (not sysc_gpsr_dbg_rst_dly0);
end if;
end process;
-- DBG D
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpsr_dbg_d_dly0 <= '0';
regs_o.gpsr_dbg_d_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpsr_dbg_d_dly0 <= sysc_gpsr_dbg_d_int;
regs_o.gpsr_dbg_d_o <= sysc_gpsr_dbg_d_int and (not sysc_gpsr_dbg_d_dly0);
end if;
end process;
-- DBG EN
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpsr_dbg_en_dly0 <= '0';
regs_o.gpsr_dbg_en_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpsr_dbg_en_dly0 <= sysc_gpsr_dbg_en_int;
regs_o.gpsr_dbg_en_o <= sysc_gpsr_dbg_en_int and (not sysc_gpsr_dbg_en_dly0);
end if;
end process;
-- Status LED
process (clk_sys_i, rst_n_i)
begin
......@@ -476,6 +548,45 @@ begin
end process;
-- DBG rst
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_dbg_rst_dly0 <= '0';
regs_o.gpcr_dbg_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpcr_dbg_rst_dly0 <= sysc_gpcr_dbg_rst_int;
regs_o.gpcr_dbg_rst_o <= sysc_gpcr_dbg_rst_int and (not sysc_gpcr_dbg_rst_dly0);
end if;
end process;
-- DBG D
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_dbg_d_dly0 <= '0';
regs_o.gpcr_dbg_d_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpcr_dbg_d_dly0 <= sysc_gpcr_dbg_d_int;
regs_o.gpcr_dbg_d_o <= sysc_gpcr_dbg_d_int and (not sysc_gpcr_dbg_d_dly0);
end if;
end process;
-- DBG EN
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
sysc_gpcr_dbg_en_dly0 <= '0';
regs_o.gpcr_dbg_en_o <= '0';
elsif rising_edge(clk_sys_i) then
sysc_gpcr_dbg_en_dly0 <= sysc_gpcr_dbg_en_int;
regs_o.gpcr_dbg_en_o <= sysc_gpcr_dbg_en_int and (not sysc_gpcr_dbg_en_dly0);
end if;
end process;
-- Memory size
-- Timer Divider
-- Timer Enable
......
modules/wrc_core/wrc_syscon_wb.wb
View file @ e44976ee
......@@ -128,6 +128,27 @@ peripheral {
align = 9;
};
field {
name = "DBG rst";
prefix = "dbg_rst";
type = MONOSTABLE;
align = 10;
};
field {
name = "DBG D";
prefix = "dbg_d";
type = MONOSTABLE;
align = 11;
};
field {
name = "DBG EN";
prefix = "dbg_en";
type = MONOSTABLE;
align = 12;
};
};
reg {
......@@ -180,6 +201,28 @@ peripheral {
align = 9;
};
field {
name = "DBG rst";
prefix = "dbg_rst";
type = MONOSTABLE;
align = 10;
};
field {
name = "DBG D";
prefix = "dbg_d";
type = MONOSTABLE;
align = 11;
};
field {
name = "DBG EN";
prefix = "dbg_en";
type = MONOSTABLE;
align = 12;
};
};
reg {
......
modules/wrc_core/wrcore_pkg.vhd
View file @ e44976ee
......@@ -220,7 +220,10 @@ package wrcore_pkg is
uart_txd_o : out std_logic;
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0)
owr_i : in std_logic_vector(1 downto 0);
debug_sr_rst_o : out std_logic;
debug_sr_d_o : out std_logic;
debug_sr_en_o : out std_logic
);
end component;
......
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