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White Rabbit core collection
Commit e59ec3ed authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'tom-new-softpll' 

Conflicts:
	modules/wr_softpll_ng/wr_softpll_ng.vhd
parents 0aafd085 52a169e7
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Showing with 1435 additions and 715 deletions
Manifest.py
View file @ e59ec3ed
......@@ -9,9 +9,10 @@ modules = {"local" :
"modules/wr_endpoint",
"modules/wr_pps_gen",
"modules/wr_dacs",
"modules/wr_si57x_interface",
"modules/wr_eca",
"modules/wr_tlu",
"modules/wrc_core",
"platform" ],
"platform"],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"
}
modules/wr_si57x_interface/Manifest.py 0 → 100644
View file @ e59ec3ed
files = ["si570_if_wbgen2_pkg.vhd",
"si570_if_wb.vhd",
"wr_si57x_interface.vhd",
"xwr_si57x_interface.vhd"]
modules/wr_si57x_interface/si570_if_wb.vhd 0 → 100644
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This diff is collapsed.
modules/wr_si57x_interface/si570_if_wb.wb 0 → 100644
View file @ e59ec3ed
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "silabs interface";
hdl_entity = "si570_if_wb";
prefix = "si570";
reg {
name = "RFREQ low part";
prefix = "RFREQL";
field {
name = "RFREQ low part";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "RFREQ hi part";
prefix = "RFREQH";
field {
name = "RFREQ hi part";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "GPIO Set/Readback Register";
prefix = "GPSR";
field {
name = "SIlabs I2C bitbanged SCL";
prefix = "scl";
description = "write 1: Set FMC SCL line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "SIlabs I2C bitbanged SDA";
prefix = "sda";
description = "write 1: Set FMC SDA line to 1 (pullup)\
read : returns the current status of the SCL line.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "GPIO Clear Register";
prefix = "GPCR";
field {
name = "SILabs I2C bitbanged SCL";
prefix = "scl";
description = "write 1: Set SCL line to 0\
read : returns the current status of the SCL line.";
type = MONOSTABLE;
};
field {
name = "SIlabs I2C bitbanged SDA";
prefix = "sda";
description = "write 1: Set SDA line to 0\
read : returns the current status of the SCL line.";
type = MONOSTABLE;
};
};
};
modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd 0 → 100644
View file @ e59ec3ed
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for silabs interface
---------------------------------------------------------------------------------------
-- File : si570_if_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from si570_if_wb.wb
-- Created : Tue Mar 19 13:39:45 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE si570_if_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package si570_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_si570_in_registers is record
gpsr_scl_i : std_logic;
gpsr_sda_i : std_logic;
end record;
constant c_si570_in_registers_init_value: t_si570_in_registers := (
gpsr_scl_i => '0',
gpsr_sda_i => '0'
);
-- Output registers (WB slave -> user design)
type t_si570_out_registers is record
rfreql_o : std_logic_vector(31 downto 0);
rfreqh_o : std_logic_vector(7 downto 0);
gpsr_scl_o : std_logic;
gpsr_scl_load_o : std_logic;
gpsr_sda_o : std_logic;
gpsr_sda_load_o : std_logic;
gpcr_scl_o : std_logic;
gpcr_sda_o : std_logic;
end record;
constant c_si570_out_registers_init_value: t_si570_out_registers := (
rfreql_o => (others => '0'),
rfreqh_o => (others => '0'),
gpsr_scl_o => '0',
gpsr_scl_load_o => '0',
gpsr_sda_o => '0',
gpsr_sda_load_o => '0',
gpcr_scl_o => '0',
gpcr_sda_o => '0'
);
function "or" (left, right: t_si570_in_registers) return t_si570_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body si570_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_si570_in_registers) return t_si570_in_registers is
variable tmp: t_si570_in_registers;
begin
tmp.gpsr_scl_i := f_x_to_zero(left.gpsr_scl_i) or f_x_to_zero(right.gpsr_scl_i);
tmp.gpsr_sda_i := f_x_to_zero(left.gpsr_sda_i) or f_x_to_zero(right.gpsr_sda_i);
return tmp;
end function;
end package body;
modules/wr_si57x_interface/wr_si57x_interface.vhd 0 → 100644
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modules/wr_si57x_interface/xwr_si57x_interface.vhd 0 → 100644
View file @ e59ec3ed
-------------------------------------------------------------------------------
-- Title : Silicon Labs Si57x oscillator I2C controller
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : xwr_si57x_interface.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2013-03-19
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Description: Wrapper for wr_si57x_interface using Wishbone records in
-- entity interface. See wr_si57x_interface.vhd for description.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
entity xwr_si57x_interface is
generic (
g_simulation : integer := 0);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
tm_dac_value_i : in std_logic_vector(23 downto 0) := x"000000";
tm_dac_value_wr_i : in std_logic := '0';
scl_pad_oen_o : out std_logic;
sda_pad_oen_o : out std_logic;
scl_pad_i : in std_logic;
sda_pad_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
);
end xwr_si57x_interface;
architecture wrapper of xwr_si57x_interface is
component wr_si57x_interface
generic (
g_simulation : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
tm_dac_value_i : in std_logic_vector(23 downto 0) := x"000000";
tm_dac_value_wr_i : in std_logic := '0';
scl_pad_oen_o : out std_logic;
sda_pad_oen_o : out std_logic;
scl_pad_i : in std_logic;
sda_pad_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic);
end component;
begin -- wrapper
U_Wrapped_si57x : wr_si57x_interface
generic map (
g_simulation => g_simulation)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
tm_dac_value_i => tm_dac_value_i,
tm_dac_value_wr_i => tm_dac_value_wr_i,
scl_pad_oen_o => scl_pad_oen_o,
sda_pad_oen_o => sda_pad_oen_o,
scl_pad_i => scl_pad_i,
sda_pad_i => sda_pad_i,
wb_adr_i => slave_i.adr,
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_sel_i => slave_i.sel,
wb_we_i => slave_i.we,
wb_cyc_i => slave_i.cyc,
wb_stb_i => slave_i.stb,
wb_ack_o => slave_o.ack,
wb_err_o => slave_o.err,
wb_stall_o => slave_o.stall);
end wrapper;
modules/wr_softpll_ng/Manifest.py
View file @ e59ec3ed
......@@ -3,4 +3,5 @@ files = ["spll_period_detect.vhd",
"spll_wbgen2_pkg.vhd",
"wr_softpll_ng.vhd",
"xwr_softpll_ng.vhd",
"softpll_pkg.vhd",
"spll_wb_slave.vhd"]
modules/wr_softpll_ng/softpll_pkg.vhd 0 → 100644
View file @ e59ec3ed
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package softpll_pkg is
constant c_softpll_max_aux_clocks : integer := 8;
type t_softpll_phase_detector_type is (CH_DDMTD, CH_BANGBANG);
type t_softpll_channel_config_array is array(0 to c_softpll_max_aux_clocks-1) of t_softpll_phase_detector_type;
constant c_softpll_default_channel_config : t_softpll_channel_config_array := (others => CH_DDMTD);
-- External 10 MHz input divider parameters.
constant c_softpll_ext_div_ref : integer := 8;
constant c_softpll_ext_div_fb : integer := 50;
constant c_softpll_ext_log2_gating : integer := 13;
end package;
package body softpll_pkg is
end softpll_pkg;
modules/wr_softpll_ng/spll_bangbang_pd.vhd
View file @ e59ec3ed
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-06-14
-- Last update: 2012-04-16
-- Last update: 2013-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -32,9 +32,6 @@ use work.gencores_pkg.all;
entity spll_bangbang_pd is
generic(
g_log2_gating : integer;
g_feedback_divider : integer;
g_ref_divider : integer;
g_error_bits : integer
);
port (
......@@ -56,6 +53,14 @@ entity spll_bangbang_pd is
rst_n_fbck_i : in std_logic;
rst_n_sysclk_i : in std_logic;
-------------------------------------------------------------------------------
-- Configuration
-------------------------------------------------------------------------------
cfg_div_ref_i: in std_logic_vector(5 downto 0);
cfg_div_fb_i: in std_logic_vector(5 downto 0);
cfg_gating_i: in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------
-- I/O
-------------------------------------------------------------------------------
......@@ -79,7 +84,7 @@ end spll_bangbang_pd;
architecture rtl of spll_bangbang_pd is
signal gate_counter : unsigned(g_log2_gating downto 0);
signal gate_counter : unsigned(15 downto 0);
signal gate_p : std_logic;
signal ph_sreg_delay : std_logic_vector(4 downto 0);
......@@ -99,8 +104,8 @@ architecture rtl of spll_bangbang_pd is
-- divider counters
signal div_ctr_fbck : unsigned(15 downto 0);
signal div_ctr_ref : unsigned(15 downto 0);
signal div_ctr_fbck : unsigned(5 downto 0);
signal div_ctr_ref : unsigned(5 downto 0);
-- disable RAM extraction (XST is trying to implement the phase detector in a
-- RAM)
......@@ -139,7 +144,7 @@ begin -- rtl
-- the divider itself
if (div_ctr_ref = g_ref_divider) then
if (div_ctr_ref = unsigned(cfg_div_ref_i)) then
div_ctr_ref <= to_unsigned(1, div_ctr_ref'length);
pd_in_ref <= not pd_in_ref;
else
......@@ -159,7 +164,7 @@ begin -- rtl
div_ctr_fbck <= to_unsigned(1, div_ctr_fbck'length);
pd_in_fbck <= '0';
else
if (div_ctr_fbck = g_feedback_divider) then
if (div_ctr_fbck = unsigned(cfg_div_fb_i)) then
div_ctr_fbck <= to_unsigned(1, div_ctr_fbck'length);
pd_in_fbck <= not pd_in_fbck; -- divide the clock :)
else
......@@ -263,8 +268,10 @@ begin -- rtl
-- decodes the PD_GATE field from PCR register and generates the gating pulse
-- on gate_p.
phase_gating_decode : process (gate_counter)
variable decoded_gating : integer;
begin
if(gate_counter(gate_counter'length-1) = '1') then
decoded_gating := to_integer(unsigned(cfg_gating_i));
if(gate_counter(decoded_gating) = '1') then
gate_p <= '1';
else
gate_p <= '0';
......
modules/wr_softpll_ng/spll_wb_slave.vhd
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modules/wr_softpll_ng/spll_wb_slave.wb
View file @ e59ec3ed
......@@ -9,16 +9,15 @@ peripheral {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Unused (kept for software compatibility).";
prefix = "UNUSED0";
size = 6;
type = CONSTANT;
value = 0;
};
field {
align = 8;
name = "Period detector reference select";
prefix = "PER_SEL";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
align = 8;
......@@ -41,11 +40,11 @@ peripheral {
};
field {
name = "Enable Period Measurement";
prefix = "PER_EN";
name = "Debug queue supported";
prefix = "DBG_SUPPORTED";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -110,37 +109,8 @@ peripheral {
};
---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
field {
name = "DMTD Clock Undersampling Divider";
prefix = "GATE_DIV";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reference Channel Undersampling Enable Register";
prefix = "RCGER";
field {
name = "Reference Channel Undersampling Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
};
};
reg {
align = 4;
name = "Output Channel Control Register";
prefix = "OCCR";
......@@ -162,10 +132,20 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Output Channel Phase Detector Type";
description = "Phase detector type used by corresponding output: 0 = DDMTD, 1 = BangBang";
prefix = "OUT_DET_TYPE";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Reference Channel Enable Register";
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
field {
......@@ -181,7 +161,7 @@ peripheral {
};
reg {
name = "Output Channel Enable Register";
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
field {
......@@ -196,32 +176,8 @@ peripheral {
};
};
reg {
name = "HPLL Period Error";
prefix = "PER_HPLL";
field {
name = "Period error value";
prefix = "ERROR";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
field {
name = "Period Error Valid";
prefix = "VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
reg {
align = 8;
name = "Helper DAC Output";
prefix = "DAC_HPLL";
......@@ -253,7 +209,7 @@ peripheral {
};
reg {
name = "Deglitcher threshold";
name = "DDMTD Deglitcher threshold";
prefix = "DEGLITCH_THR";
field {
......@@ -318,12 +274,14 @@ peripheral {
};
};
fifo_reg {
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
size = 8192;
optional = "g_with_debug_fifo";
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
......@@ -373,6 +331,42 @@ peripheral {
};
};
reg {
name = "Aux clock configuration register";
prefix = "AUX_CR";
field {
name = "Aux output select";
prefix = "AUX_SEL";
size = 3;
type = PASS_THROUGH;
};
field {
name = "BB reference divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_REF";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB feedback divider";
description = "Reference clock division factor. Applicable only for aux channels with BB phase detector.";
prefix = "DIV_FB";
size = 6;
type = PASS_THROUGH;
};
field {
name = "BB gating frequency select";
description = "BB detector output gating frequency. GATE = log2(period in clk_ref cycles).";
prefix = "GATE";
size = 4;
type = PASS_THROUGH;
};
};
irq {
......
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ e59ec3ed
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu Feb 14 10:46:40 2013
-- Created : Thu Jul 25 11:14:53 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -23,14 +23,14 @@ package spll_wbgen2_pkg is
type t_spll_in_registers is record
csr_n_ref_i : std_logic_vector(5 downto 0);
csr_n_out_i : std_logic_vector(2 downto 0);
csr_dbg_supported_i : std_logic;
eccr_ext_supported_i : std_logic;
eccr_align_done_i : std_logic;
eccr_ext_ref_present_i : std_logic;
occr_out_en_i : std_logic_vector(7 downto 0);
occr_out_det_type_i : std_logic_vector(7 downto 0);
rcer_i : std_logic_vector(31 downto 0);
ocer_i : std_logic_vector(7 downto 0);
per_hpll_error_i : std_logic_vector(15 downto 0);
per_hpll_valid_i : std_logic;
crr_in_i : std_logic_vector(31 downto 0);
crr_out_i : std_logic_vector(15 downto 0);
dfr_host_wr_req_i : std_logic;
......@@ -45,14 +45,14 @@ package spll_wbgen2_pkg is
constant c_spll_in_registers_init_value: t_spll_in_registers := (
csr_n_ref_i => (others => '0'),
csr_n_out_i => (others => '0'),
csr_dbg_supported_i => '0',
eccr_ext_supported_i => '0',
eccr_align_done_i => '0',
eccr_ext_ref_present_i => '0',
occr_out_en_i => (others => '0'),
occr_out_det_type_i => (others => '0'),
rcer_i => (others => '0'),
ocer_i => (others => '0'),
per_hpll_error_i => (others => '0'),
per_hpll_valid_i => '0',
crr_in_i => (others => '0'),
crr_out_i => (others => '0'),
dfr_host_wr_req_i => '0',
......@@ -67,13 +67,8 @@ package spll_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_spll_out_registers is record
csr_per_sel_o : std_logic_vector(5 downto 0);
csr_per_en_o : std_logic;
eccr_ext_en_o : std_logic;
eccr_align_en_o : std_logic;
dccr_gate_div_o : std_logic_vector(5 downto 0);
rcger_gate_sel_o : std_logic_vector(31 downto 0);
rcger_gate_sel_wr_o : std_logic;
occr_out_lock_o : std_logic_vector(7 downto 0);
rcer_o : std_logic_vector(31 downto 0);
rcer_load_o : std_logic;
......@@ -99,16 +94,19 @@ package spll_wbgen2_pkg is
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
aux_cr_aux_sel_o : std_logic_vector(2 downto 0);
aux_cr_aux_sel_wr_o : std_logic;
aux_cr_div_ref_o : std_logic_vector(5 downto 0);
aux_cr_div_ref_wr_o : std_logic;
aux_cr_div_fb_o : std_logic_vector(5 downto 0);
aux_cr_div_fb_wr_o : std_logic;
aux_cr_gate_o : std_logic_vector(3 downto 0);
aux_cr_gate_wr_o : std_logic;
end record;
constant c_spll_out_registers_init_value: t_spll_out_registers := (
csr_per_sel_o => (others => '0'),
csr_per_en_o => '0',
eccr_ext_en_o => '0',
eccr_align_en_o => '0',
dccr_gate_div_o => (others => '0'),
rcger_gate_sel_o => (others => '0'),
rcger_gate_sel_wr_o => '0',
occr_out_lock_o => (others => '0'),
rcer_o => (others => '0'),
rcer_load_o => '0',
......@@ -133,7 +131,15 @@ package spll_wbgen2_pkg is
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0'
trr_wr_empty_o => '0',
aux_cr_aux_sel_o => (others => '0'),
aux_cr_aux_sel_wr_o => '0',
aux_cr_div_ref_o => (others => '0'),
aux_cr_div_ref_wr_o => '0',
aux_cr_div_fb_o => (others => '0'),
aux_cr_div_fb_wr_o => '0',
aux_cr_gate_o => (others => '0'),
aux_cr_gate_wr_o => '0'
);
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -166,14 +172,14 @@ variable tmp: t_spll_in_registers;
begin
tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_i);
tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
tmp.csr_dbg_supported_i := f_x_to_zero(left.csr_dbg_supported_i) or f_x_to_zero(right.csr_dbg_supported_i);
tmp.eccr_ext_supported_i := f_x_to_zero(left.eccr_ext_supported_i) or f_x_to_zero(right.eccr_ext_supported_i);
tmp.eccr_align_done_i := f_x_to_zero(left.eccr_align_done_i) or f_x_to_zero(right.eccr_align_done_i);
tmp.eccr_ext_ref_present_i := f_x_to_zero(left.eccr_ext_ref_present_i) or f_x_to_zero(right.eccr_ext_ref_present_i);
tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);
tmp.occr_out_det_type_i := f_x_to_zero(left.occr_out_det_type_i) or f_x_to_zero(right.occr_out_det_type_i);
tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
tmp.per_hpll_error_i := f_x_to_zero(left.per_hpll_error_i) or f_x_to_zero(right.per_hpll_error_i);
tmp.per_hpll_valid_i := f_x_to_zero(left.per_hpll_valid_i) or f_x_to_zero(right.per_hpll_valid_i);
tmp.crr_in_i := f_x_to_zero(left.crr_in_i) or f_x_to_zero(right.crr_in_i);
tmp.crr_out_i := f_x_to_zero(left.crr_out_i) or f_x_to_zero(right.crr_out_i);
tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i);
......
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ e59ec3ed
This diff is collapsed.
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ e59ec3ed
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-29
-- Last update: 2012-07-09
-- Last update: 2013-07-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -15,7 +15,7 @@
-- Struct'ized version of wr_softpll_ng.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
-- Copyright (c) 2012-2013 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -40,6 +40,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.softpll_pkg.all;
entity xwr_softpll_ng is
generic(
......@@ -55,12 +56,6 @@ entity xwr_softpll_ng is
g_num_ref_inputs : integer := 1;
g_num_outputs : integer := 1;
-- When true, an additional period detector is provided, measuring the
-- frequency offset between the DDMTD clock and a chosen reference input clock.
-- The feature is not required by the current version of the SoftPLL servo
-- algorithm, but is kept for testing/debugging purposes.
g_with_period_detector : boolean := false;
-- When true, an additional FIFO is instantiated, providing a realtime record
-- of user-selectable SoftPLL parameters (e.g. tag values, phase error, DAC drive).
-- These values can be read by "spll_dbg_proxy" daemon for further analysis.
......@@ -71,12 +66,6 @@ entity xwr_softpll_ng is
-- (e.g. GPSDO/Cesium 10 MHz)
g_with_ext_clock_input : boolean := false;
-- When true, the SoftPLL can undersample measured signals by dividing the DMTD
-- clock by a progammable ratio, so that one can perform phase shift
-- measurements of clocks with frequencies different than the base rate of the
-- DMTD oscillator.
g_with_undersampling : boolean := false;
-- When true, DDMTD inputs are reverse (so that the DDMTD offset clocks is
-- being sampled by the measured clock). This is functionally equivalent to
-- "direct" operation, but may improve FPGA timing/routability.
......@@ -85,16 +74,10 @@ entity xwr_softpll_ng is
-- Divides the DDMTD clock inputs by 2, removing the "CLOCK_DEDICATED_ROUTE"
-- errors under ISE tools, at the cost of bandwidth reduction. Use with care.
g_divide_input_by_2 : boolean := false;
-- Bang Bang phase detector parameters:
-- reference divider
g_bb_ref_divider : integer := 1;
-- feedback divider
g_bb_feedback_divider : integer := 1;
-- phase error measurement gating
g_bb_log2_gating : integer := 10;
-- Configuration of all output channels (phase detector type & dividers). See
-- softpll_pkg.vhd for details.
g_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE
......@@ -144,22 +127,16 @@ end xwr_softpll_ng;
architecture wrapper of xwr_softpll_ng is
component wr_softpll_ng
generic (
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_with_period_detector : boolean;
g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean;
g_with_undersampling : boolean;
g_reverse_dmtds : boolean;
g_divide_input_by_2 : boolean;
g_bb_ref_divider : integer;
g_bb_feedback_divider : integer;
g_bb_log2_gating : integer;
g_channels_config : t_softpll_channel_config_array;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
......@@ -201,14 +178,10 @@ begin -- behavioral
g_num_ref_inputs => g_num_ref_inputs,
g_num_outputs => g_num_outputs,
g_with_debug_fifo => g_with_debug_fifo,
g_with_period_detector => g_with_period_detector,
g_with_undersampling => g_with_undersampling,
g_with_ext_clock_input => g_with_ext_clock_input,
g_reverse_dmtds => g_reverse_dmtds,
g_divide_input_by_2 => g_divide_input_by_2,
g_bb_ref_divider => g_bb_ref_divider,
g_bb_feedback_divider => g_bb_feedback_divider,
g_bb_log2_gating => g_bb_log2_gating
g_channels_config => g_channels_config
)
port map (
clk_sys_i => clk_sys_i,
......
modules/wrc_core/wr_core.vhd
View file @ e59ec3ed
......@@ -3,9 +3,9 @@
-------------------------------------------------------------------------------
-- File : wr_core.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma Elektronika, CERN BE-CO-HT
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2013-03-19
-- Last update: 2013-03-20
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -66,6 +66,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wrcore_pkg.all;
......@@ -74,6 +75,7 @@ use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.softpll_pkg.all;
entity wr_core is
generic(
......@@ -90,7 +92,9 @@ entity wr_core is
g_dpram_size : integer := 90112/4; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false
);
port(
---------------------------------------------------------------------------
......@@ -241,11 +245,11 @@ entity wr_core is
tm_link_up_o : out std_logic;
-- DAC Control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- Aux clock lock enable
tm_clk_aux_lock_en_i : in std_logic := '0';
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- Aux clock locked flag
tm_clk_aux_locked_o : out std_logic;
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- Timecode output
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
......@@ -498,19 +502,13 @@ begin
g_with_ext_clock_input => g_with_external_clock_input,
g_reverse_dmtds => false,
g_divide_input_by_2 => true,
g_with_undersampling => false,
g_with_period_detector => false,
g_with_debug_fifo => true,
g_bb_ref_divider => 8,
g_bb_feedback_divider => 50,
g_bb_log2_gating => 13,
g_tag_bits => 22,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_ref_inputs => 1,
g_num_outputs => 1 + g_aux_clks)
g_with_debug_fifo => g_softpll_enable_debugger,
g_tag_bits => 22,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_ref_inputs => 1,
g_num_outputs => 1 + g_aux_clks,
g_channels_config => g_softpll_channels_config)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_net_n,
......@@ -548,16 +546,26 @@ begin
clk_fb(0) <= clk_ref_i;
clk_fb(g_aux_clks downto 1) <= clk_aux_i;
out_enable(0) <= '1';
out_enable(g_aux_clks downto 1) <= (others => tm_clk_aux_lock_en_i);
out_enable(g_aux_clks downto 1) <= tm_clk_aux_lock_en_i;
dac_dpll_data_o <= dac_dpll_data;
dac_dpll_load_p1_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"0") else '0';
tm_dac_value_o <= x"00" & dac_dpll_data;
tm_dac_wr_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"1") else '0';
p_decode_dac_writes : process(dac_dpll_load_p1, dac_dpll_sel)
begin
for i in 0 to g_aux_clks-1 loop
if dac_dpll_sel = std_logic_vector(to_unsigned(i+1, 4)) then
tm_dac_wr_o(i) <= dac_dpll_load_p1;
else
tm_dac_wr_o(i) <= '0';
end if;
end loop; -- i
end process;
locked_spll : if g_aux_clks > 0 generate
tm_clk_aux_locked_o <= spll_out_locked(1); -- !!! what if more than one clock?! FIXME
tm_clk_aux_locked_o <= spll_out_locked(g_aux_clks downto 1);
end generate;
softpll_irq <= spll_wb_out.int;
......
modules/wrc_core/wrcore_pkg.vhd
View file @ e59ec3ed
......@@ -7,6 +7,7 @@ use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.softpll_pkg.all;
package wrcore_pkg is
......@@ -238,7 +239,7 @@ package wrcore_pkg is
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"65158dc0",
version => x"00000001",
version => x"00000002",
date => x"20120305",
name => "WR-Soft-PLL ")));
component xwr_softpll_ng
......@@ -246,17 +247,13 @@ package wrcore_pkg is
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_with_period_detector : boolean := false;
g_with_debug_fifo : boolean := false;
g_with_ext_clock_input : boolean := false;
g_with_undersampling : boolean := false;
g_reverse_dmtds : boolean := false;
g_bb_ref_divider : integer := 1;
g_bb_feedback_divider : integer := 1;
g_bb_log2_gating : integer := 1;
g_divide_input_by_2 : boolean := false;
g_with_debug_fifo : boolean := false;
g_with_ext_clock_input : boolean := false;
g_reverse_dmtds : boolean := false;
g_divide_input_by_2 : boolean := false;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
g_address_granularity : t_wishbone_address_granularity;
g_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -297,7 +294,9 @@ package wrcore_pkg is
g_dpram_size : integer := 90112/4; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false
);
port(
clk_sys_i : in std_logic;
......@@ -363,9 +362,9 @@ package wrcore_pkg is
tm_link_up_o : out std_logic;
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic := '0';
tm_clk_aux_locked_o : out std_logic;
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
......@@ -394,7 +393,9 @@ package wrcore_pkg is
g_dpram_size : integer := 90112/4; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false
);
port(
---------------------------------------------------------------------------
......@@ -543,13 +544,12 @@ package wrcore_pkg is
-----------------------------------------
tm_link_up_o : out std_logic;
-- DAC Control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
-- Aux clock lock enable
tm_clk_aux_lock_en_i : in std_logic := '0';
-- Aux clock locked flag
tm_clk_aux_locked_o : out std_logic;
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0) ;
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0) ;
-- Timecode output
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
......
modules/wrc_core/xwr_core.vhd
View file @ e59ec3ed
......@@ -4,9 +4,9 @@
-------------------------------------------------------------------------------
-- File : wr_core.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma Elektronika, CERN BE-CO-HT
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2013-02-19
-- Last update: 2013-02-08
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -59,6 +59,7 @@ use work.wishbone_pkg.all;
use work.endpoint_pkg.all;
use work.wr_fabric_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.softpll_pkg.all;
entity xwr_core is
......@@ -76,7 +77,9 @@ entity xwr_core is
g_dpram_size : integer := 90112/4; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_softpll_channels_config : t_softpll_channel_config_array := c_softpll_default_channel_config;
g_softpll_enable_debugger : boolean := false
);
port(
---------------------------------------------------------------------------
......@@ -189,11 +192,11 @@ entity xwr_core is
tm_link_up_o : out std_logic;
-- DAC Control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- Aux clock lock enable
tm_clk_aux_lock_en_i : in std_logic := '0';
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- Aux clock locked flag
tm_clk_aux_locked_o : out std_logic;
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
-- Timecode output
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
......@@ -210,136 +213,6 @@ entity xwr_core is
end xwr_core;
architecture struct of xwr_core is
component wr_core is
generic(
g_simulation : integer := 0;
g_phys_uart : boolean := true;
g_virtual_uart : boolean := false;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 1;
g_rx_buffer_size : integer := 12;
g_dpram_initf : string := "";
g_dpram_size : integer := 16384; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_i : in std_logic;
pps_ext_i : in std_logic;
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
scl_o : out std_logic;
scl_i : in std_logic;
sda_o : out std_logic;
sda_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_sda_i : in std_logic;
sfp_det_i : in std_logic;
btn1_i : in std_logic;
btn2_i : in std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
owr_pwren_o : out std_logic_vector(1 downto 0);
owr_en_o : out std_logic_vector(1 downto 0);
owr_i : in std_logic_vector(1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
aux_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
aux_we_o : out std_logic := '0';
aux_cyc_o : out std_logic := '0';
aux_stb_o : out std_logic := '0';
aux_ack_i : in std_logic;
aux_stall_i : in std_logic;
ext_snk_adr_i : in std_logic_vector(1 downto 0) := "00";
ext_snk_dat_i : in std_logic_vector(15 downto 0) := x"0000";
ext_snk_sel_i : in std_logic_vector(1 downto 0) := "00";
ext_snk_cyc_i : in std_logic := '0';
ext_snk_we_i : in std_logic := '0';
ext_snk_stb_i : in std_logic := '0';
ext_snk_ack_o : out std_logic;
ext_snk_err_o : out std_logic;
ext_snk_stall_o : out std_logic;
ext_src_adr_o : out std_logic_vector(1 downto 0);
ext_src_dat_o : out std_logic_vector(15 downto 0);
ext_src_sel_o : out std_logic_vector(1 downto 0);
ext_src_cyc_o : out std_logic;
ext_src_stb_o : out std_logic;
ext_src_we_o : out std_logic;
ext_src_ack_i : in std_logic := '1';
ext_src_err_i : in std_logic := '0';
ext_src_stall_i : in std_logic := '0';
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_frame_id_o : out std_logic_vector(15 downto 0);
txtsu_ts_value_o : out std_logic_vector(31 downto 0);
txtsu_ts_incorrect_o : out std_logic;
txtsu_stb_o : out std_logic;
txtsu_ack_i : in std_logic;
tm_link_up_o : out std_logic;
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic;
tm_clk_aux_lock_en_i : in std_logic;
tm_clk_aux_locked_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
pps_p_o : out std_logic;
pps_led_o : out std_logic;
dio_o : out std_logic_vector(3 downto 0);
rst_aux_n_o : out std_logic;
link_ok_o : out std_logic
);
end component;
begin
WRPC : wr_core
......@@ -354,7 +227,9 @@ begin
g_dpram_size => g_dpram_size,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_aux_sdb => g_aux_sdb)
g_aux_sdb => g_aux_sdb,
g_softpll_channels_config => g_softpll_channels_config,
g_softpll_enable_debugger => g_softpll_enable_debugger)
port map(
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
......@@ -451,16 +326,16 @@ begin
txtsu_stb_o => timestamps_o.stb,
txtsu_ack_i => timestamps_ack_i,
tm_link_up_o => tm_link_up_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
tm_link_up_o => tm_link_up_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
dio_o => dio_o,
rst_aux_n_o => rst_aux_n_o,
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ e59ec3ed
......@@ -16,7 +16,7 @@ package wr_xilinx_pkg is
g_simulation : integer := 0);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
ch0_tx_disparity_o : out std_logic;
......@@ -26,8 +26,8 @@ package wr_xilinx_pkg is
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
......
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