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White Rabbit core collection
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White Rabbit core collection
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ed3204cc
Commit
ed3204cc
authored
Jan 18, 2019
by
Grzegorz Daniluk
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platform_xilinx: separate locked output for sys_pll
parent
7c8ec4b7
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5 changed files
with
6 additions
and
6 deletions
+6
-6
wr_cute_pkg.vhd
board/cute/wr_cute_pkg.vhd
+1
-1
xwrc_board_cute.vhd
board/cute/xwrc_board_cute.vhd
+2
-2
Manifest.py
modules/timing/Manifest.py
+1
-1
cute_core_ref_top.vhd
top/cute_ref_design/cute_core_ref_top.vhd
+1
-1
cute_wr_ref_top.vhd
top/cute_ref_design/cute_wr_ref_top.vhd
+1
-1
No files found.
board/cute/wr_cute_pkg.vhd
View file @
ed3204cc
...
...
@@ -173,7 +173,7 @@ package wr_cute_pkg is
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pll_
locked_o
:
out
std_logic
;
pll_
aux_locked_o
:
out
std_logic
;
link_ok_o
:
out
std_logic
);
end
component
xwrc_board_cute
;
...
...
board/cute/xwrc_board_cute.vhd
View file @
ed3204cc
...
...
@@ -275,7 +275,7 @@ entity xwrc_board_cute is
pps_p_o
:
out
std_logic
;
pps_led_o
:
out
std_logic
;
pps_csync_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
;
pll_
aux_
locked_o
:
out
std_logic
;
-- Link ok indication
link_ok_o
:
out
std_logic
);
...
...
@@ -426,6 +426,7 @@ begin -- architecture struct
clk_20m_o
=>
clk_pll_20m
,
clk_62m5_dmtd_o
=>
clk_pll_dmtd
,
pll_locked_o
=>
pll_locked
,
pll_aux_locked_o
=>
pll_aux_locked_o
,
clk_10m_ext_o
=>
clk_10m_ext
,
phy8_o
=>
phy8_to_wrc
,
phy8_i
=>
phy8_from_wrc
,
...
...
@@ -674,7 +675,6 @@ begin -- architecture struct
link_ok_o
=>
link_ok_o
);
tm_time_valid_o
<=
tm_time_valid
;
pll_locked_o
<=
pll_locked
;
onewire_oen_o
<=
onewire_en
(
0
);
onewire_in
(
0
)
<=
onewire_i
;
...
...
modules/timing/Manifest.py
View file @
ed3204cc
...
...
@@ -3,6 +3,6 @@ files = ["dmtd_phase_meas.vhd",
"multi_dmtd_with_deglitcher.vhd"
,
"hpll_period_detect.vhd"
,
"pulse_gen.vhd"
,
"oserdes_4_to_1"
,
"oserdes_4_to_1
.vhd
"
,
"pulse_stamper.vhd"
]
top/cute_ref_design/cute_core_ref_top.vhd
View file @
ed3204cc
...
...
@@ -312,7 +312,7 @@ begin
pps_p_o
=>
pps_out
,
pps_led_o
=>
usr_led1
,
pps_csync_o
=>
pps_csync
,
pll_
locked_o
=>
pll_locked
,
pll_
aux_locked_o
=>
pll_locked
,
link_ok_o
=>
usr_led2
);
cnx_slave_in
<=
cnx_master_out
;
...
...
top/cute_ref_design/cute_wr_ref_top.vhd
View file @
ed3204cc
...
...
@@ -325,7 +325,7 @@ begin
pps_p_o
=>
pps_out
,
pps_led_o
=>
usr_led1
,
pps_csync_o
=>
pps_csync
,
pll_
locked_o
=>
pll_locked
,
pll_
aux_locked_o
=>
pll_locked
,
link_ok_o
=>
usr_led2
);
cnx_slave_in
<=
cnx_master_out
;
...
...
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