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White Rabbit core collection
Commit f408609e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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modules/wrsw_nic: fixed interface bugs (dreqs at wrong moments and wrong offset of port_id in OOB)

parent 23add6ef
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modules/wrsw_nic/nic_rx_fsm.vhd
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...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT -- Company : CERN BE-Co-HT
-- Created : 2010-11-24 -- Created : 2010-11-24
-- Last update: 2012-01-19 -- Last update: 2012-01-24
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -48,7 +48,8 @@ entity nic_rx_fsm is ...@@ -48,7 +48,8 @@ entity nic_rx_fsm is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Wishbone regs -- Wishbone regs
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
bna_i: in std_logic;
regs_i : in t_nic_out_registers; regs_i : in t_nic_out_registers;
regs_o : out t_nic_in_registers; regs_o : out t_nic_in_registers;
...@@ -243,7 +244,7 @@ begin ...@@ -243,7 +244,7 @@ begin
state <= RX_WAIT_SOF; -- and start waiting for state <= RX_WAIT_SOF; -- and start waiting for
-- incoming traffic -- incoming traffic
else else
rx_dreq_mask <= '0'; -- disable RX (/dev/null) rx_dreq_mask <= bna_i; -- enable RX (but to /dev/null)
end if; end if;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -367,7 +368,7 @@ begin ...@@ -367,7 +368,7 @@ begin
-- the descriptor -- the descriptor
if(oob_sreg (0) = '1') then -- 1st OOB word if(oob_sreg (0) = '1') then -- 1st OOB word
cur_rx_desc.port_id <= '0' & fab_in.data(15 downto 11); cur_rx_desc.port_id <= '0' & fab_in.data(4 downto 0);
end if; end if;
if(oob_sreg (1) = '1') then -- 2nd OOB word if(oob_sreg (1) = '1') then -- 2nd OOB word
...@@ -478,7 +479,7 @@ begin ...@@ -478,7 +479,7 @@ begin
-- the condition below forces the RX FSM to go into RX_MEM_RESYNC state. Don't -- the condition below forces the RX FSM to go into RX_MEM_RESYNC state. Don't
-- receive anything during the RESYNC cycle. -- receive anything during the RESYNC cycle.
elsif(rx_rdreg_toggle = '1' and buf_grant_i = '1' and state /= RX_WAIT_SOF) then elsif(rx_rdreg_toggle = '1' and buf_grant_i = '1' and (state /= RX_WAIT_SOF) and (state /= RX_REQUEST_DESCRIPTOR)) then
fab_dreq <= '0'; fab_dreq <= '0';
else else
fab_dreq <= '1'; fab_dreq <= '1';
......
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