- 07 Apr, 2020 4 commits
-
-
Maciej Lipinski authored
It seems that pll_aux_locked is in clk_sys clock domain. When synthesising cute for BTrain I had timing errors in the 10MHz generation process. This commit fixes the timing issues.
-
Maciej Lipinski authored
1) bugfix: - tm_time_valid_i signal from ref_clk domain was used in sys_clk to gate statistics in xrx_streamers_stats.vhd - likely this gating was not needed because statistics are done when rcvd_latency_valid_i is true and this should be true only when time is valid, anyway - added gc_sync_ffs to synchronize tm_time_valid_i to sys_clk (added in xrtx_streamers_stats.vhd 2) new feature - added initial reset of statistics when the WR node is first synchronized after powerup/reset. - this is useful so that we have a valid reset timestamp without a need for a management tool to reset them. So far, when a device was started, the reset timestamp was zero, so without additional action of reseting stats, it was not possible to know when the stats were started
-
Maciej Lipinski authored
TAI time is sampled from clk_ref to clk_sys domain. Apparently, such sampling sometimes takes more than the configured 20 periods. Likely, this is not a problem, but the updated gc_synchronizer2 now complains. So, I increased the sampling time to 30 periods.
-
Maciej Lipinski authored
When g_num_exts=0, the input of xwr_softpll_ng clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0); was of wrong range, i.e. std_logic_vector(-1 to 0). Function f_nonzero_vector() was added to generate std_logic_vector(0 to 0) in the case when g_num_exts=0.
-
- 03 Apr, 2020 1 commit
-
-
Grzegorz Daniluk authored
-
- 30 Jan, 2020 1 commit
-
-
Grzegorz Daniluk authored
Compilation and synthesis run at any new push. Simulation run according to CI schedule configured on OHWR.
-
- 28 Jan, 2020 5 commits
-
-
Grzegorz Daniluk authored
-
Pascal Bos authored
-
Peter Jansweijer authored
upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file; use generic g_direct_dmtd
-
Peter Jansweijer authored
add wrpc/wrc_phy16_direct_dmtd.bram (spll KP parameters times 5 due to VCXOs range 20 ppm, incremented mode master lock timeout) wrc_phy16_direct_dmtd.bram build with: wrpc-sw.git peter_direct_dmtd SHA 50f1c0e ppsi.git peter_direct_dmtd SHA bf5f6de
-
Peter Jansweijer authored
-
- 20 Jan, 2020 1 commit
-
-
Tomasz Wlostowski authored
-
- 17 Dec, 2019 6 commits
-
-
Grzegorz Daniluk authored
-
Miguel Jimenez Lopez authored
-
Miguel Jimenez Lopez authored
-
Miguel Jimenez Lopez authored
- Add generic parameter for the SDB info of the auxiliary interface of the WRPC. - Export pps_csync and pps_valid ports from the WRPC.
-
Miguel Jimenez Lopez authored
wr_nic_wrapper: Fix copyright issues.
-
Miguel Jimenez Lopez authored
Fix a place & route error related to the OBUF used for PPS output signal.
-
- 09 Dec, 2019 1 commit
-
-
Grzegorz Daniluk authored
-
- 12 Nov, 2019 1 commit
-
-
Tomasz Wlostowski authored
-
- 30 Aug, 2019 16 commits
-
-
Grzegorz Daniluk authored
-
Grzegorz Daniluk authored
-
Grzegorz Daniluk authored
-
Tomasz Wlostowski authored
-
Grzegorz Daniluk authored
-
Grzegorz Daniluk authored
It's used only locally in dmtd sampler. We don't have enough global clock nets in Virtex6 for 18-port version of WRS.
-
Grzegorz Daniluk authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
- 20 Aug, 2019 1 commit
-
-
Grzegorz Daniluk authored
-
- 13 Aug, 2019 1 commit
-
-
Grzegorz Daniluk authored
-
- 08 Aug, 2019 2 commits
-
-
Grzegorz Daniluk authored
-
Grzegorz Daniluk authored
-