- we now use Cheby for the MDIO register layout (small changes in the naming)
- dropped LPC_CTRL/LPC_STAT registers in favour of a full WB master interface to the PHY.

wr_endpoint: assume Endpoint's private sub-cores are always present. No need to declare them as components.

platform/wr_gtp_phy: Kintex7 LPDC now has a proper WB interface for the LPDC/Xilinx DRP registers. Follow up in the Endpoint/PCS HDL in the subsequent commits

no upper bound for etherbone

It occurred (using Vivado 2021.2) that, when disconnecting the fiber from a timeTransmitter
to a WR node timeReceiver, the link was not be up when re-establishing the connection.
In a disconnect situation rx_cdr_lock starts to toggle (~2x '1', 2x '0' @ 16ns) which was
undetected due to rx_cdr_lock_filtered.