Second attempt to use dual reset async fifos and pulse synchronizers. The first one was 9810ef9a,
later on reverted by 93d49e1f, because it was causing sync problems when unplugging/replugging the
fiber.

The problem was in the endpoint's rx path, where one side of the reset (the rx_clk side) was taking
into account the state of the PHY (via the phy_rdy_i signal), while the other side (the sys_clk
side) was not. This has been fixed in this commit, by using phy_rdy_i as an active-low reset source
for both clock domains of the rx path.

Tested on an SPEC, works.