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Grzegorz Daniluk authored
This reverts commit 21c67bc8. DCM is much more jittery than PLL_BASE: DCM_SP: 125MHz -> 62.5MHz: pk-to-pk jitter: 300ps 125MHz -> 125MHz: pk-to-pk jitter: 200ps 20MHz -> 62.5MHz: pk-to-pk jitter: 1772ps (!!!!) PLL_BASE: 125MHz -> 62.5MHz: pk-to-pk jitter: 185ps 125MHz-> 125MHz: pk-to-pk jitter 161ps 20MHz -> 62.5MHz: pk-to-pk jitter 417ps
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Manifest.py | ||
wr_svec_pkg.vhd | ||
wrc_board_svec.vhd | ||
xwrc_board_svec.vhd |