Commit 1bd30289 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl: initial commit

parent dc92d265
`define ADDR_DDS_CR 6'h0
`define DDS_CR_TEST_OFFSET 0
`define DDS_CR_TEST 32'h00000001
`define DDS_CR_SLAVE_OFFSET 1
`define DDS_CR_SLAVE 32'h00000002
`define DDS_CR_MASTER_OFFSET 2
`define DDS_CR_MASTER 32'h00000004
`define DDS_CR_ADC_BB_ENABLE_OFFSET 3
`define DDS_CR_ADC_BB_ENABLE 32'h00000008
`define DDS_CR_CLK_ID_OFFSET 4
`define DDS_CR_CLK_ID 32'h000ffff0
`define ADDR_DDS_GPIOR 6'h4
`define DDS_GPIOR_PLL_SYS_CS_N_OFFSET 0
`define DDS_GPIOR_PLL_SYS_CS_N 32'h00000001
`define DDS_GPIOR_PLL_SYS_RESET_N_OFFSET 1
`define DDS_GPIOR_PLL_SYS_RESET_N 32'h00000002
`define DDS_GPIOR_PLL_SCLK_OFFSET 2
`define DDS_GPIOR_PLL_SCLK 32'h00000004
`define DDS_GPIOR_PLL_SDIO_OFFSET 3
`define DDS_GPIOR_PLL_SDIO 32'h00000008
`define DDS_GPIOR_PLL_SDIO_DIR_OFFSET 4
`define DDS_GPIOR_PLL_SDIO_DIR 32'h00000010
`define DDS_GPIOR_PLL_VCXO_RESET_N_OFFSET 5
`define DDS_GPIOR_PLL_VCXO_RESET_N 32'h00000020
`define DDS_GPIOR_PLL_VCXO_CS_N_OFFSET 6
`define DDS_GPIOR_PLL_VCXO_CS_N 32'h00000040
`define DDS_GPIOR_PLL_VCXO_FUNCTION_OFFSET 7
`define DDS_GPIOR_PLL_VCXO_FUNCTION 32'h00000080
`define DDS_GPIOR_PLL_VCXO_SDO_OFFSET 8
`define DDS_GPIOR_PLL_VCXO_SDO 32'h00000100
`define DDS_GPIOR_ADF_CE_OFFSET 9
`define DDS_GPIOR_ADF_CE 32'h00000200
`define DDS_GPIOR_ADF_CLK_OFFSET 10
`define DDS_GPIOR_ADF_CLK 32'h00000400
`define DDS_GPIOR_ADF_LE_OFFSET 11
`define DDS_GPIOR_ADF_LE 32'h00000800
`define DDS_GPIOR_ADF_DATA_OFFSET 12
`define DDS_GPIOR_ADF_DATA 32'h00001000
`define DDS_GPIOR_ADC_SDI_OFFSET 13
`define DDS_GPIOR_ADC_SDI 32'h00002000
`define DDS_GPIOR_ADC_CNV_OFFSET 14
`define DDS_GPIOR_ADC_CNV 32'h00004000
`define DDS_GPIOR_ADC_SCK_OFFSET 15
`define DDS_GPIOR_ADC_SCK 32'h00008000
`define DDS_GPIOR_ADC_SDO_OFFSET 16
`define DDS_GPIOR_ADC_SDO 32'h00010000
`define ADDR_DDS_FREQ_HI 6'h8
`define ADDR_DDS_FREQ_LO 6'hc
`define ADDR_DDS_GAIN 6'h10
`define ADDR_DDS_RSTR 6'h14
`define DDS_RSTR_PLL_RST_OFFSET 0
`define DDS_RSTR_PLL_RST 32'h00000001
`define DDS_RSTR_SW_RST_OFFSET 1
`define DDS_RSTR_SW_RST 32'h00000002
`define ADDR_DDS_I2CR 6'h18
`define DDS_I2CR_SCL_OUT_OFFSET 0
`define DDS_I2CR_SCL_OUT 32'h00000001
`define DDS_I2CR_SDA_OUT_OFFSET 1
`define DDS_I2CR_SDA_OUT 32'h00000002
`define DDS_I2CR_SCL_IN_OFFSET 2
`define DDS_I2CR_SCL_IN 32'h00000004
`define DDS_I2CR_SDA_IN_OFFSET 3
`define DDS_I2CR_SDA_IN 32'h00000008
`define ADDR_DDS_PIR 6'h1c
`define DDS_PIR_KP_OFFSET 0
`define DDS_PIR_KP 32'h0000ffff
`define DDS_PIR_KI_OFFSET 16
`define DDS_PIR_KI 32'hffff0000
`define ADDR_DDS_PD_FIFO_R0 6'h20
`define DDS_PD_FIFO_R0_DATA_OFFSET 0
`define DDS_PD_FIFO_R0_DATA 32'h0000ffff
`define ADDR_DDS_PD_FIFO_CSR 6'h24
`define DDS_PD_FIFO_CSR_FULL_OFFSET 16
`define DDS_PD_FIFO_CSR_FULL 32'h00010000
`define DDS_PD_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_PD_FIFO_CSR_EMPTY 32'h00020000
`define ADDR_DDS_TUNE_FIFO_R0 6'h28
`define DDS_TUNE_FIFO_R0_DATA_OFFSET 0
`define DDS_TUNE_FIFO_R0_DATA 32'hffffffff
`define ADDR_DDS_TUNE_FIFO_CSR 6'h2c
`define DDS_TUNE_FIFO_CSR_FULL_OFFSET 16
`define DDS_TUNE_FIFO_CSR_FULL 32'h00010000
`define DDS_TUNE_FIFO_CSR_EMPTY_OFFSET 17
`define DDS_TUNE_FIFO_CSR_EMPTY 32'h00020000
files = ["dds_single_channel.v","lfsr_gen.vhd" ]
files = ["dds_stage.v", "pi_control.v", "dds_quad_channel.v", "mdsp.v", "dds_wb_slave.vhd", "dds_wbgen2_pkg.vhd", "max5870_serializer.vhd", "dds_core.vhd", "cic_1024x.vhd", "spi_master.vhd", "ad7980_if.vhd","timestamp_adder.vhd" ]
modules = {"local":"streamers"}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dds_wbgen2_pkg.all;
entity ad7980_if is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trig_i : in std_logic;
d_o : out std_logic_vector(15 downto 0);
d_valid_o : out std_logic;
adc_sdo_i : in std_logic;
adc_sck_o : out std_logic;
adc_cnv_o : out std_logic;
adc_sdi_o : out std_logic
);
end ad7980_if;
architecture rtl of ad7980_if is
component spi_master
generic (
g_div_ratio_log2 : integer;
g_num_data_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
drdy_o : out std_logic;
ready_o : out std_logic;
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
signal count : unsigned(7 downto 0);
signal do_acq : std_logic;
type t_state is (WAIT_TRIG, START_CNV, READBACK);
signal state : t_state;
signal d_rdy : std_logic;
begin -- rtl
U_SPI_Master : spi_master
generic map (
g_div_ratio_log2 => 3,
g_num_data_bits => 16)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
start_i => do_acq,
cpol_i => '0',
data_i => x"0000",
data_o => d_o,
drdy_o => d_rdy,
spi_sclk_o => adc_sck_o,
spi_miso_i => adc_sdo_i);
d_valid_o <= d_rdy;
adc_sdi_o <= '1';
p_acquire : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= (others => '0');
adc_cnv_o <= '0';
do_acq <= '0';
state <= WAIT_TRIG;
else
case state is
when WAIT_TRIG =>
if(trig_i = '1') then
count <= (others => '0');
adc_cnv_o <= '1';
state <= START_CNV;
end if;
when START_CNV =>
count<= count +1;
if(count = 100) then
adc_cnv_o <= '0';
do_acq <= '1';
state <= READBACK;
end if;
when READBACK =>
do_acq <= '0';
if(d_rdy = '1') then
state <= WAIT_TRIG;
end if;
end case;
end if;
end if;
end process;
end rtl;
#!/bin/bash
wbgen2 -V dds_wb_slave.vhd -H record -p dds_wbgen2_pkg.vhd -K ../dds_regs.vh -s defines -C dds_regs.h -D doc/dds_regs.html dds_wb_slave.wb
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`timescale 1ns/1ps
module dds_quad_channel
(
clk_i,
rst_n_i,
acc_i,
acc_o,
dreq_i,
tune_i,
tune_load_i,
acc_load_i,
y0_o,
y1_o,
y2_o,
y3_o);
parameter integer g_acc_frac_bits = 32;
parameter integer g_output_bits = 14;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 10;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_lut_cell_size = g_lut_sample_bits + g_lut_slope_bits;
input clk_i;
input rst_n_i;
input acc_load_i;
input tune_load_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
output reg [g_acc_frac_bits + g_lut_size_log2 : 0] acc_o;
input [g_acc_frac_bits + g_lut_size_log2 : 0] tune_i;
input dreq_i;
output wire [g_output_bits-1:0] y0_o, y1_o, y2_o, y3_o;
wire [g_lut_size_log2-1:0] lut_addr[0:3];
reg [c_lut_cell_size-1:0] lut_data[0:3];
reg [c_acc_bits-1:0] acc, acc_d0, acc_f[0:3], tune;
wire [g_output_bits-1:0] y[0:3];
always@(posedge clk_i)
begin
if(!rst_n_i)begin
tune <= 0;
acc <= 0;
end else begin
if(tune_load_i)
tune <= tune_i;
if(acc_load_i)
acc <= acc_i;
else if(dreq_i) begin
acc <= acc + tune;
acc_d0 <= acc;
acc_o <= acc;
acc_f[0] <= acc_d0;
acc_f[1] <= acc_d0 + (tune >> 2);
acc_f[2] <= acc_d0 + (tune >> 1);
acc_f[3] <= acc_d0 + (tune >> 2) + (tune >> 1);
end
end // else: !if(!rst_n_i)
end // always@ (posedge clk_i)
generate
genvar i;
for(i=0;i<4;i=i+1)
begin
dds_stage
#(
.g_acc_frac_bits(g_acc_frac_bits),
.g_output_bits(g_output_bits),
.g_lut_size_log2(g_lut_size_log2),
.g_dither_init_value(i*1234567)
)
U_Stage_X
(
.clk_i(clk_i),
.rst_n_i(rst_n_i),
.acc_i(acc_f[i]),
.y_o(y[i]),
.dreq_i(dreq_i),
.lut_addr_o(lut_addr[i]),
.lut_data_i(lut_data[i])
);
end // for (i=0;i<4;i++)
endgenerate
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut01[0:2**g_lut_size_log2-1];
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut23[0:2**g_lut_size_log2-1];
`include "lut_init.v"
initial begin
`INIT_LUT(01)
`INIT_LUT(23)
end
always@(posedge clk_i)
lut_data[0] <= lut01[lut_addr[0]];
always@(posedge clk_i)
lut_data[1] <= lut01[lut_addr[1]];
always@(posedge clk_i)
lut_data[2] <= lut23[lut_addr[2]];
always@(posedge clk_i)
lut_data[3] <= lut23[lut_addr[3]];
assign y0_o = y[0];
assign y1_o = y[1];
assign y2_o = y[2];
assign y3_o = y[3];
endmodule // dds_quad_channel
\ No newline at end of file
`timescale 1ns/1ps
module dds_stage
(
clk_i,
rst_n_i,
acc_i,
dreq_i,
y_o,
lut_addr_o,
lut_data_i
);
parameter integer g_acc_frac_bits = 32;
parameter integer g_dither_init_value = 32'h00000001;
parameter integer g_output_bits = 12;
parameter integer g_lut_sample_bits= 18;
parameter integer g_lut_slope_bits = 18;
parameter integer g_interp_shift = 7;
parameter integer g_lut_size_log2 = 12;
parameter integer g_dither_taps = 32'hD0000001;
parameter integer g_dither_length = 32;
localparam c_dither_bits = (g_lut_sample_bits - g_output_bits - 1);
localparam c_acc_bits = g_acc_frac_bits + g_lut_size_log2 + 1;
localparam c_output_shift = g_lut_sample_bits - g_output_bits;
wire signed [c_dither_bits :0 ] dither_in;
input clk_i;
input rst_n_i;
input [g_acc_frac_bits + g_lut_size_log2 : 0] acc_i;
input dreq_i;
output reg [g_output_bits-1:0] y_o;
output reg [g_lut_size_log2-1:0] lut_addr_o;
input [g_lut_sample_bits + g_lut_slope_bits - 1:0] lut_data_i;
reg [c_acc_bits-1:0] acc0, acc1, tune;
wire [g_lut_size_log2 : 0] phase;
wire [g_lut_slope_bits-1 : 0] frac;
reg [g_lut_slope_bits-1 : 0] frac_d0, frac_d1, frac_d2, frac_d3;
wire half;
reg [g_lut_size_log2-1:0] addr0, addr1,tmp,tmp2,tmp3;
reg [8:0] sign;
reg [g_lut_sample_bits + g_lut_slope_bits-1:0] lut_in;
wire signed [g_lut_slope_bits-1:0] lut_slope;
reg signed [g_lut_slope_bits-1:0] slope_d0;
wire signed [g_lut_sample_bits-1:0] lut_sample;
reg signed [g_lut_sample_bits-1:0] sample_d0;
reg signed [g_lut_sample_bits-1:0] interp, interp_d0;
reg signed [g_lut_sample_bits-1:0] qv;
reg signed [g_output_bits:0] yt;
wire signed [2*g_lut_slope_bits-1:0] interp_mul;
reg [g_dither_length-1:0] lfsr=g_dither_init_value;
assign lut_slope = lut_in[g_lut_sample_bits + g_lut_slope_bits - 1 : g_lut_sample_bits ];
assign lut_sample = lut_in[g_lut_sample_bits - 1 : 0];
assign phase = acc_i [ g_acc_frac_bits + g_lut_size_log2 - 1 : g_acc_frac_bits - 1];
assign half = acc_i [g_acc_frac_bits + g_lut_size_log2];
assign frac = acc_i [g_acc_frac_bits - 1 : g_acc_frac_bits-g_lut_slope_bits];
always@(posedge clk_i)
begin
if (!rst_n_i) begin
lfsr <= g_dither_init_value;
end else if (dreq_i) begin
if(lfsr[0])
lfsr <= {1'b0, lfsr[g_dither_length-1:1]} ^ g_dither_taps;
else
lfsr <= {1'b0, lfsr[g_dither_length-1:1]};
end
end
wire signed [g_lut_slope_bits:0] interp_frac;
assign interp_frac = {1'b0, frac_d3};
assign dither_in = { lfsr[c_dither_bits+4:5], 1'b0 };
assign interp_mul = lut_slope * interp_frac;
always@(posedge clk_i)
begin
if (!rst_n_i) begin
end else if(dreq_i) begin
addr0 <= acc_i[g_acc_frac_bits + g_lut_size_log2-1 : g_acc_frac_bits];
sign <= {sign[7:0], half };
lut_addr_o <= addr0;
lut_in <= lut_data_i;
frac_d0 <= frac;
frac_d1 <= frac_d0;
frac_d2 <= frac_d1;
frac_d3 <= frac_d2;
interp <= interp_mul >>> (g_lut_slope_bits + g_interp_shift);
sample_d0 <= lut_sample;
qv <= (sample_d0) + (interp) + (dither_in) + 1;
if(sign[5])
yt <= qv >>> (c_output_shift-1);
else
yt <= (-qv) >>> (c_output_shift-1);
if(yt[0])
y_o <= (yt[g_output_bits:1] + (1<<(g_output_bits - 1)) + 1);
else
y_o <= (yt[g_output_bits:1] + (1<<(g_output_bits - 1)));
end // if (dreq_i)
end // always@ (posedge clk_i)
endmodule // dds_single_channel
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "DDS RF distribution WB Slave";
hdl_entity = "dds_wb_slave";
prefix = "dds";
reg {
prefix = "CR";
name = "Control Register";
field {
name = "Enable DDS test mode";
prefix = "TEST";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Enable DDS RF slave mode";
prefix = "SLAVE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Enable DDS RF master mode";
prefix = "MASTER";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "ADC Bitbanged Access Enable";
prefix = "ADC_BB_ENABLE";
type = MONOSTABLE;
};
field {
name = "Broadcast Clock ID";
description = "Send/Receive clocks matching given ID";
prefix = "CLK_ID";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
};
};
reg {
prefix = "GPIOR";
name = "GPIO register";
field {
name = "System PLL CS";
prefix = "PLL_SYS_CS_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "System Reset";
prefix = "PLL_SYS_RESET_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL SCLK (shared)";
prefix = "PLL_SCLK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL SDIO (shared)";
prefix = "PLL_SDIO";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "PLL SDIO direction (shared)";
prefix = "PLL_SDIO_DIR";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Reset";
prefix = "PLL_VCXO_RESET_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Chip Select";
prefix = "PLL_VCXO_CS_N";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL Function";
prefix = "PLL_VCXO_FUNCTION";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "VCXO PLL SDO";
prefix = "PLL_VCXO_SDO";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "ADF4002 Chip Enable";
prefix = "ADF_CE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Clock";
prefix = "ADF_CLK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Latch Enable";
prefix = "ADF_LE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADF4002 Data";
prefix = "ADF_DATA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Data Out";
prefix = "ADC_SDI";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Convert Strobe";
prefix = "ADC_CNV";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Serial Clock";
prefix = "ADC_SCK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "AD7980 Bitbanged Data In";
prefix = "ADC_SDO";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
fifo_reg {
name = "PD ADC Test FIFO (test mode)";
prefix = "PD_FIFO";
size = 512;
direction = CORE_TO_BUS;
clock = "clk_ref_i";
flags_bus = { FIFO_EMPTY, FIFO_FULL };
flags_dev = { FIFO_EMPTY, FIFO_FULL };
field {
name = "ADC data";
prefix = "DATA";
size = 16;
type = SLV;
};
};
fifo_reg {
name = "DDS Tuning FIFO (test mode)";
prefix = "TUNE_FIFO";
size = 512;
flags_bus = { FIFO_EMPTY, FIFO_FULL };
flags_dev = { FIFO_EMPTY };
direction = BUS_TO_CORE;
clock = "clk_ref_i";
field {
name = "DDS tune word";
prefix = "DATA";
size = 32;
type = SLV;
};
};
reg {
name = "DDS Center frequency hi";
prefix = "FREQ_HI";
field {
name = "Center freq HI";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DDS Center frequency lo";
prefix = "FREQ_LO";
field {
name = "Center freq LO";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};