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White Rabbit Network Interface Card
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3694eff9
Commit
3694eff9
authored
Jul 16, 2013
by
Benoit Rat
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syn: add generic_reset to xise project
parent
6abde584
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1 changed file
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9 additions
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4 deletions
+9
-4
wr_nic.xise
syn/spec/wr_nic.xise
+9
-4
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syn/spec/wr_nic.xise
View file @
3694eff9
...
...
@@ -46,7 +46,7 @@
<property
xil_pn:name=
"Change Device Speed To"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To Post Trace"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Combinatorial Logic Optimization"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"
non-
default"
/>
<property
xil_pn:name=
"Compile SIMPRIM (Timing) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile UNISIM (Functional) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile XilinxCoreLib (CORE Generator) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
...
...
@@ -56,7 +56,7 @@
<property
xil_pn:name=
"Configuration Rate spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Correlate Output to Input Design"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create ASCII Configuration File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"true"
xil_pn:valueState=
"
non-
default"
/>
<property
xil_pn:name=
"Create Bit File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create I/O Pads from Ports"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create IEEE 1532 Configuration File spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -200,6 +200,7 @@
<property
xil_pn:name=
"Package"
xil_pn:value=
"fgg484"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Timing-Driven Packing and Placement"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place & Route Effort Level (Overall)"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place And Route Mode"
xil_pn:value=
"Normal Place and Route"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place MultiBoot Settings into Bitstream spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -315,7 +316,7 @@
<property
xil_pn:name=
"Wait for DCM and PLL Lock (Output Events) spartan6"
xil_pn:value=
"Default (NoWait)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wakeup Clock spartan6"
xil_pn:value=
"Startup Clock"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0xFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"
non-
default"
/>
<property
xil_pn:name=
"Write Timing Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
...
...
@@ -1217,10 +1218,14 @@
<file
xil_pn:name=
"../../top/spec/wr_nic_sdb_top.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"293"
/>
</file>
<file
xil_pn:name=
"../../top/spec/spec_reset_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"345"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"345"
/>
</file>
</files>
<bindings/>
<version
xil_pn:ise_version=
"14.
5
"
xil_pn:schema_version=
"2"
/>
<version
xil_pn:ise_version=
"14.
4
"
xil_pn:schema_version=
"2"
/>
</project>
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