Commit 98933e52 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Miguel Jimenez Lopez

kernel: synced up registers' headers with the most recent HDL, removed obsolete files

parent 75a74920
# This Makefile is used to reproduce the headers from svn checkout.
# You need to have "wbgen2" in your command search path and the white-rabbit
# svn checkout in $SVN. Since this is only meant to be used by me,
# no serious checking is done
# List of input files in SVN checkout
MODULES = $(SVN)/trunk/hdl/modules
SPECS = $(SVN)/trunk/documentation/specifications
WB_ENDPOINT = $(MODULES)/wrsw_endpoint/ep_wishbone_controller.wb
WB_PPSG = $(MODULES)/wrsw_pps_gen/wrsw_pps_gen.wb
WB_CALIB = $(MODULES)/wrsw_calibrator_dmtd/wrsw_calibrator_dmtd.wb
WB_TSTAMP = $(MODULES)/wrsw_txtsu/wrsw_txtsu.wb
WB_RTU = $(MODULES)/wrsw_rtu/wrsw_rtu_wb.wb
WB_NIC = $(SPECS)/hdlspec/WRSW_wbc_internal_NIC/wr_nic.wb
HEADERS = endpoint-regs.h ppsg-regs.h calib-regs.h tstamp-regs.h rtu-regs.h \
nic-regs.h
# repos (wr-cores and wr-switch-hdl) Git checkout in $REPOS.
# Since this is only meant to be used by me (or Tom) no serious checking is done.
# List of input files in Git checkout
MODULES_WRS ?= $(REPOS)/wr-switch-hdl/modules
MODULES_WRC ?= $(REPOS)/wr-hdl/modules
#SPECS = $(HW_REPO)/trunk/documentation/specifications
WB_ENDPOINT = $(MODULES_WRC)/wr_endpoint/ep_wishbone_controller.wb
WB_MDIO = $(MODULES_WRC)/wr_endpoint/pcs_regs.wb
WB_PPSG = $(MODULES_WRC)/wr_pps_gen/pps_gen_wb.wb
WB_TSTAMP = $(MODULES_WRS)/wrsw_txtsu/wrsw_txtsu.wb
WB_RTU = $(MODULES_WRS)/wrsw_rtu/rtu_wishbone_slave.wb
WB_NIC = $(MODULES_WRS)/wrsw_nic/wr_nic.wb
WB_SOFTPLL = $(MODULES_WRC)/wr_softpll/wr_softpll.wb
HEADERS = endpoint-regs.h endpoint-mdio.h ppsg-regs.h tstamp-regs.h rtu-regs.h \
nic-regs.h softpll-regs.h
WBINPUT = $(HEADERS:.h=wb)
# No default, for people who types "make" everywhere (like me)
......@@ -28,7 +32,7 @@ headers: $(HEADERS)
%.h: %.wb
wbgen2 --cstyle=struct --co=$@ $<
sed -i 's,inttypes.h,linux/types.h,' $@
sed -i 's,#include <inttypes.h>,#ifdef __KERNEL__\n#include <linux/types.h>\n#else\n#include <stdint.h>\n#endif\n,' $@
sed -i '/ Created *: .*20[0-9][0-9]$$/ d' $@
sed -i 's/-REGS_WB//' $@
......@@ -37,9 +41,10 @@ headers: $(HEADERS)
# Do it silent so errors stand out
wbinput:
@cp $(WB_ENDPOINT) endpoint-regs.wb
@cp $(WB_MDIO) endpoint-mdio.wb
@cp $(WB_PPSG) ppsg-regs.wb
@cp $(WB_CALIB) calib-regs.wb
@cp $(WB_TSTAMP) tstamp-regs.wb
@cp $(WB_RTU) rtu-regs.wb
@cp $(WB_NIC) nic-regs.wb
@cp $(WB_SOFTPLL) softpll-regs.wb
@echo "Copied input files from subversions to local directory"
/*
Register definitions for slave core: DMTD PHY Calibrator
* File : calib-regs.h
* Author : auto-generated by wbgen2 from calib-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE calib-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CALIB
#define __WBGEN2_REGDEFS_CALIB
#include <linux/types.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Enable in reg: Control Register */
#define DPC_CR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Compare clock select in reg: Control Register */
#define DPC_CR_IN_SEL_MASK WBGEN2_GEN_MASK(8, 4)
#define DPC_CR_IN_SEL_SHIFT 8
#define DPC_CR_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define DPC_CR_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for field: DMTD averaging samples in reg: Control Register */
#define DPC_CR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define DPC_CR_N_AVG_SHIFT 16
#define DPC_CR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define DPC_CR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Status register */
/* definitions for field: Phase shift value in reg: Status register */
#define DPC_SR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DPC_SR_PS_VAL_SHIFT 0
#define DPC_SR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DPC_SR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase shift value ready in reg: Status register */
#define DPC_SR_PS_RDY WBGEN2_GEN_MASK(24, 1)
PACKED struct DPC_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Status register */
uint32_t SR;
};
#endif
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "DMTD PHY Calibrator";
prefix = "dpc";
hdl_entity = "dmtd_calibrator_wb";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Enable";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Compare clock select";
prefix = "IN_SEL";
type = SLV;
size = 4;
align = 8;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Status register";
prefix = "SR";
field {
name = "Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
};
This diff is collapsed.
This diff is collapsed.
......@@ -13,7 +13,12 @@
#ifndef __WBGEN2_REGDEFS_ENDPOINT
#define __WBGEN2_REGDEFS_ENDPOINT
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -265,6 +270,7 @@
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BASE 0x00000080 /* base address */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
......
This diff is collapsed.
......@@ -75,10 +75,10 @@ top = peripheral {
field {
name = "Buffer Not Available";
prefix = "bna";
description = "No buffers were available when receiving a packet. Cleared by writing a one to this bit";
description = "No buffers were available when receiving a packet.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
};
......@@ -92,6 +92,57 @@ top = peripheral {
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Transmission done";
prefix = "tx_done";
description = "read 1: All non-empty TX descriptors have been transmitted\
read 0: Transmission in progress\
write 1: Clears the flag\
write 0: No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Transmission error";
prefix = "tx_error";
description = "read 1: A TX error occured and the transmission was stopped. CUR_TX_DESC is pointing the TX descriptor for which the error occured\
read 0: No TX error\
write 1: Clears the flag\
write 0: No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
align = 8;
name = "Current TX descriptor";
size = 3;
prefix = "cur_TX_Desc";
description = "Index of the currently handled TX descriptor";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 8;
name = "Current RX descriptor";
size = 3;
prefix = "cur_RX_DESC";
description = "Index of the currently handled RX descriptor";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -109,6 +160,7 @@ top = peripheral {
irq {
name = "Receive Complete";
prefix = "rcomp";
ack_line = true;
description = "A frame has been stored in memory.";
trigger = LEVEL_1;
};
......@@ -116,20 +168,17 @@ top = peripheral {
irq {
name = "Transmit Complete";
prefix = "tcomp";
ack_line = true;
mask_line = true;
description = "Frame successfully transmitted";
trigger = LEVEL_1;
};
irq {
name = "Receive Error";
prefix = "rxerr";
description = "Receive Error";
trigger = LEVEL_1;
};
irq {
name = "Transmit Error";
prefix = "txerr";
ack_line = true;
mask_line = true;
trigger = LEVEL_1;
};
......@@ -138,31 +187,30 @@ top = peripheral {
-- prefix = "dtx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- ram {
-- name = "RX descriptors mem";
-- ram {
-- name = "RX descriptors mem";
-- prefix = "drx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
ram {
name = "TX/RX Buffers";
prefix = "mem";
-- 8192 * 32 = 32Kb
size = 8192;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
ram {
name = "TX/RX Buffers";
prefix = "mem";
-- 8192 * 32 = 32Kb
size = 8192;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
......@@ -235,21 +283,20 @@ TX_desc_template =
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
-- extended the sizes to 16 bits (although the buffer is 32kB-long)
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
type = SLV;
size = 16;
size = 13;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Length of buffer in bytes";
name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
prefix = "len";
type = SLV;
size = 16;
size = 13;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -320,18 +367,17 @@ RX_desc_template = {
access_dev = WRITE_ONLY;
};
field {
name = "RX timestamp (possibly) incorrect";
prefix = "TS_INCORRECT";
description = "read 1: the RX timestamp in R2 register may be incorrect, because it has been generated during counter adjustment,\
read 0: the RX timestamp in R2 register is correct";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
field {
name = "RX Timestamp (possibly) incorrect";
prefix = "TS_INCORRECT";
align = 15;
description = "1 - there is a risk that the timestamp in RX_D2 is invalid, because it was taken during counter adjustment,\
0 - RX timestamp OK.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -342,8 +388,8 @@ RX_desc_template = {
field {
name = "RX_TS_R";
description = "Value of the RX timestamp (rising edge bits)";
prefix = "TS_R";
description = "Value of the RX timestamp (rising edge bits)";
size = 28;
type = SLV;
access_bus = READ_ONLY;
......@@ -369,7 +415,7 @@ RX_desc_template = {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
type = SLV;
size = 16;
size = 13;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
......@@ -378,7 +424,7 @@ RX_desc_template = {
name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
prefix = "len";
type = SLV;
size = 16;
size = 13;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
......
......@@ -13,7 +13,12 @@
#ifndef __WBGEN2_REGDEFS_PPSG
#define __WBGEN2_REGDEFS_PPSG
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -62,6 +67,17 @@
/* definitions for register: UTC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
......@@ -77,6 +93,8 @@ PACKED struct PPSG_WB {
uint32_t ADJ_UTCLO;
/* [0x18]: REG UTC Adjustment register (most-significant part) */
uint32_t ADJ_UTCHI;
/* [0x1c]: REG External sync control register */
uint32_t ESCR;
};
#endif
......@@ -56,6 +56,7 @@ peripheral {
clock = "refclk_i";
};
field {
name = "PPS Pulse width";
description = "Width of generated PPS pulses in 125 MHz refernce clock cycles";
......@@ -151,6 +152,46 @@ peripheral {
};
};
reg {
name = "External sync control register";
prefix = "ESCR";
field {
name = "Sync to external PPS input";
description = "write 1: Waits until a pulse on external PPS input arrives and re-synchronizes the PPS counter to it\
write 0: no effect\
read 1: external synchronization done\
read 0: external synchronization in progress";
type = BIT;
prefix = "SYNC";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "PPS output valid";
description = "write 1: PPS output provides reliable 1-PPS signal\
write 0: PPS output is invalid";
prefix = "PPS_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Timecode output(UTC+cycles) valid";
description = "write 1: Timecode output provides valid time\
write 0: Timecode output does not provide valid time";
prefix = "TM_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
};
};
......@@ -13,7 +13,12 @@
#ifndef __WBGEN2_REGDEFS_RTU
#define __WBGEN2_REGDEFS_RTU
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......
/*
Register definitions for slave core: WR Softcore PLL
* File : softpll-regs.h
* Author : auto-generated by wbgen2 from softpll-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE softpll-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SOFTPLL
#define __WBGEN2_REGDEFS_SOFTPLL
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: SPLL Control/Status Register */
/* definitions for field: Tagger enable in reg: SPLL Control/Status Register */
#define SPLL_CSR_TAG_EN_MASK WBGEN2_GEN_MASK(0, 4)
#define SPLL_CSR_TAG_EN_SHIFT 0
#define SPLL_CSR_TAG_EN_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define SPLL_CSR_TAG_EN_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Tag ready in reg: SPLL Control/Status Register */
#define SPLL_CSR_TAG_RDY_MASK WBGEN2_GEN_MASK(4, 4)
#define SPLL_CSR_TAG_RDY_SHIFT 4
#define SPLL_CSR_TAG_RDY_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define SPLL_CSR_TAG_RDY_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for field: Aux clock locking enable in reg: SPLL Control/Status Register */
#define SPLL_CSR_AUX_EN WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Aux clock locked flag (to slave) in reg: SPLL Control/Status Register */
#define SPLL_CSR_AUX_LOCK WBGEN2_GEN_MASK(9, 1)
/* definitions for register: HPLL Frequency Error */
/* definitions for register: DMPLL Tag ref */
/* definitions for register: DMPLL Tag fb */
/* definitions for register: DMPLL Tag aux */
/* definitions for register: HPLL DAC Output */
/* definitions for register: DMPLL DAC Output */
/* definitions for register: AUX DAC Output */
/* definitions for register: Deglitcher threshold */
/* definitions for register: Interrupt disable register */
/* definitions for field: Got a tag in reg: Interrupt disable register */
#define SPLL_EIC_IDR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Got a tag in reg: Interrupt enable register */
#define SPLL_EIC_IER_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Got a tag in reg: Interrupt mask register */
#define SPLL_EIC_IMR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Got a tag in reg: Interrupt status register */
#define SPLL_EIC_ISR_TAG WBGEN2_GEN_MASK(0, 1)
PACKED struct SPLL_WB {
/* [0x0]: REG SPLL Control/Status Register */
uint32_t CSR;
/* [0x4]: REG HPLL Frequency Error */
uint32_t PER_HPLL;
/* [0x8]: REG DMPLL Tag ref */
uint32_t TAG_REF;
/* [0xc]: REG DMPLL Tag fb */
uint32_t TAG_FB;
/* [0x10]: REG DMPLL Tag aux */
uint32_t TAG_AUX;
/* [0x14]: REG HPLL DAC Output */
uint32_t DAC_HPLL;
/* [0x18]: REG DMPLL DAC Output */
uint32_t DAC_DMPLL;
/* [0x1c]: REG AUX DAC Output */
uint32_t DAC_AUX;
/* [0x20]: REG Deglitcher threshold */
uint32_t DEGLITCH_THR;
/* padding to: 16 words */
uint32_t __padding_0[7];
/* [0x40]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x44]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x48]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x4c]: REG Interrupt status register */
uint32_t EIC_ISR;
};
#endif
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Softcore PLL";
hdl_entity = "softpll_wb";
prefix = "SPLL";
reg {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
name = "Tagger enable";
prefix = "TAG_EN";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Tag ready";
prefix = "TAG_RDY";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Aux clock locking enable";
prefix = "AUX_EN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Aux clock locked flag (to slave)";
prefix = "AUX_LOCK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "HPLL Frequency Error";
prefix = "PER_HPLL";
field {
name = "Period error value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
};
reg {
name = "DMPLL Tag ref";
prefix = "TAG_REF";
field {
name = "Tag value";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_ref_rd_ack_o";
};
};
reg {