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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 5535f4f3 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Marek Gumiński
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[PSU] WIP

parent 87519995
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Showing with 408 additions and 302 deletions
modules/wrsw_psu/Manifest.py
View file @ 5535f4f3
files = [
"psu_wbgen2_pkg.vhd",
"psu_wishbone_controller.vhd",
"psu_pkg.vhd",
"psu_announce_snooper.vhd",
"xwrsw_psu.vhd",
"../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd",
"../../ip_cores/general-cores/modules/common/gencores_pkg.vhd",
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd",
"../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd",
"psu_packet_injection.vhd",
"psu_tx_ctrl.vhd",
"xwrsw_psu.vhd"
]
\ No newline at end of file
modules/wrsw_psu/psu_announce_snooper.vhd
View file @ 5535f4f3
......@@ -155,6 +155,7 @@ architecture behavioral of psu_announce_snooper is
SOURCE_PORT_NUMBER,
SEQ_ID,
WAIT_CLOCK_CLASS,
EVALUATE_TX,
CLOCK_CLASS,
WAIT_EOF
);
......@@ -183,7 +184,9 @@ architecture behavioral of psu_announce_snooper is
signal duplicate : std_logic; -- the same sequence second time
signal seqIdWrong : std_logic; -- not 1 greater than previous
signal dropAnnounce : std_logic;
signal zeros : std_logic_vector(g_port_number-1 downto 0);
begin
zeros <=(others =>'0');
-- data stored in "data" is being acked by snk | data cnt is incremented
data_valid <= '1' when (snk_i.cyc = '1' and snk_i.stb = '1' and src_i.stall = '0' and snk_i.adr="00") else '0';
oob_valid <= '1' when (snk_i.cyc = '1' and snk_i.stb = '1' and src_i.stall = '0' and snk_i.adr="01") else '0';
......@@ -219,9 +222,9 @@ begin
if(state = WAIT_SOURCE_PORT_ID) then
sourcePortIDmatch <= '1';
elsif(state = SOURCE_CLOCK_ID and data_valid = '1' and rd_ram_data_i(15 downto 0) ~= data) then
elsif(state = SOURCE_CLOCK_ID and data_valid = '1' and rd_ram_data_i(15 downto 0) /= data) then
sourcePortIDmatch <= '0';
elsif(state = SOURCE_PORT_NUMBER and data_valid = '1' and rd_ram_data_i(15 downto 0) ~= data) then
elsif(state = SOURCE_PORT_NUMBER and data_valid = '1' and rd_ram_data_i(15 downto 0) /= data) then
sourcePortIDmatch <= '0';
elsif(state = WAIT_SOF) then
sourcePortIDmatch <= '0';
......@@ -233,7 +236,7 @@ begin
clockClassMatch <= '0';
end if;
if(state = SEQ_ID and data_valid = '1' and std_logic_vector(to_unsigned(data)+1) = rd_ram_data_i(15 downto 0)) then
if(state = SEQ_ID and data_valid = '1' and std_logic_vector(unsigned(data)+1) = rd_ram_data_i(15 downto 0)) then
duplicate <= '1';
elsif(state = WAIT_SOF) then
duplicate <= '0';
......@@ -275,14 +278,18 @@ begin
detected_announce_o <= '0';
if(cyc_d = '0' and snk_i.cyc ='1') then
state <= WAIT_DATA;
next_offset <= (others=>'0');
rd_ram_addr <= (others=>'0');
port_mask <= rtu_dst_port_mask_i;
detect_mask <= (others=>'0');
rd_port_info_addr <= '0';
wr_port_info_addr <= '0';
dropAnnounce <= '0';
if(g_snoop_mode = TX_SEQ_ID_MODE and (snoop_ports_mask_i & rtu_dst_port_mask_i) = zeros) then
state <= WAIT_SOF;
else
state <= WAIT_DATA;
next_offset <= (others=>'0');
rd_ram_addr <= (others=>'0');
port_mask <= rtu_dst_port_mask_i;
detect_mask <= (others=>'0');
rd_port_info_addr <= '0';
wr_port_info_addr <= '0';
dropAnnounce <= '0';
end if;
end if;
when WAIT_DATA =>
......@@ -408,31 +415,30 @@ begin
if(data_valid = '1' and word_cnt = next_offset) then
if(g_snoop_mode = TX_SEQ_ID_MODE) then
state <= EVALUATE_TX;
detect_mask(g_port_number-1 downto 0) <= port_mask;
detect_mask(31 downto g_port_number) <= (others =>'0');
detected_announce_o <= '1';
else
state <= WAIT_EOF;
end if;
end if;
when EVALUATE_TX =>
if(holdover_on = '1' and (clockClassMatch ='0' or duplicate '1' or seqIdWrong='1'')) then
state <= WAIT_SOF;
dropAnnounce <= '1'
else
state <= WAIT_EOF;
if(holdover_on_i = '1' and (clockClassMatch ='0' or duplicate = '1' or seqIdWrong ='1')) then
dropAnnounce <= '1';
end if;
state <= WAIT_EOF;
when WAIT_EOF =>
if(oob_valid = '1' or (cyc_d = '1' and snk_i.cyc = '0' )) then -- 1st OOB word
state <= WAIT_SOF;
dropAnnounce <= '0';
if(dropAnnounce = '0') then
sel <= not sel;
end if;
if(oob_valid = '1' and g_snoop_mode = RX_CLOCK_CLASS_MODE) then
detect_mask <= f_onehot_encode(data(4 downto 0));
detected_announce_o <= '1';
if(oob_valid = '1' and g_snoop_mode = RX_CLOCK_CLASS_MODE) then
detect_mask <= f_onehot_encode(data(4 downto 0));
elsif(g_snoop_mode = TX_SEQ_ID_MODE) then
detect_mask(g_port_number-1 downto 0) <= port_mask;
detect_mask(31 downto g_port_number) <= (others =>'0');
end if;
end if;
end if;
......@@ -444,28 +450,29 @@ begin
end process;
word_rd <= word_cnt +1;
rd_ram_addr_o <= '1' & "000" & port_index & rd_port_info_addr when ((word_cnt = next_offset and state = SOURCE_CLOCK_ID) or state = SOURCE_PORT_NUMBER) else
rd_ram_addr_o <= '1' & sel & "00" & port_index & rd_port_info_addr when ((word_cnt = next_offset and state = SOURCE_CLOCK_ID) or state = SOURCE_PORT_NUMBER) else
'0' & sel & std_logic_vector(word_rd);
wr_ram_addr_o <= '1' & "000" & port_index & wr_port_info_addr when (state = SOURCE_PORT_NUMBER or state = SEQ_ID) else
wr_ram_addr_o <= '1' & not sel & "00" & port_index & wr_port_info_addr when (state = SOURCE_PORT_NUMBER or state = SEQ_ID) else
'0' & not sel & std_logic_vector(word_cnt);
wr_ram_data_o(15 downto 0) <= std_logic_vector(to_unsigned(data) + 1) when data_valid = '1'and state = SEQ_ID) else
data when (data_valid = '1') else
wr_ram_data_o(15 downto 0) <= std_logic_vector(unsigned(data) + 1) when (data_valid = '1' and state = SEQ_ID) else
data when (data_valid = '1') else
(others =>'0');
wr_ram_data_o(17) <= '1' when (state = CLOCK_CLASS) else '0';
-- start of PTP announce msg
wr_ram_data_o(17) <= '1' when (state = WAIT_MSG_TYPE and
data_valid = '1' and
word_cnt = next_offset and
data(11 downto 8) = x"B" and
data(3 downto 0) = x"2") else
'0';
-- wr_ram_data_o(17) <= '1' when (state = WAIT_MSG_TYPE and
-- data_valid = '1' and
-- word_cnt = next_offset and
-- data(11 downto 8) = x"B" and
-- data(3 downto 0) = x"2") else
-- '0';
-- valid data (to somehow pass info when the frame finishes (without having to register)
wr_ram_data_o(16) <= data_valid;
wr_ram_ena_o <= data_valid;
wr_ram_ena_o <= data_valid;
rxtx_detected_mask_o <= detect_mask(g_port_number-1 downto 0);
srcdst_port_mask_o <= detect_mask(g_port_number-1 downto 0);
wr_ram_sel_o <= sel;
rd_ram_sel_o <= not sel;
......@@ -477,7 +484,7 @@ begin
src_o.we <= snk_i.we;
src_o.sel <= snk_i.sel;
snk_o.ack <= src_i.ack;
snk_o.ack <= src_i.ack when (dropAnnounce = '0') else '1';
snk_o.stall <= src_i.stall;
snk_o.err <= src_i.err;
snk_o.rty <= src_i.rty;
......
modules/wrsw_psu/psu_packet_injection.vhd
View file @ 5535f4f3
......@@ -53,11 +53,14 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.endpoint_private_pkg.all;
use work.psu_pkg.all;
use work.wr_fabric_pkg.all;
-- use work.endpoint_private_pkg.all;
entity psu_packet_injection is
generic(
g_port_number : integer:=18
);
port
(
clk_sys_i : in std_logic;
......@@ -70,52 +73,62 @@ entity psu_packet_injection is
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
rtu_dst_port_mask_o : out std_logic_vector(g_port_number-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
rtu_dst_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
rtu_prio_i : in std_logic_vector(2 downto 0);
rtu_drop_i : in std_logic;
rtu_rsp_valid_i : in std_logic;
rtu_rsp_ack_o : out std_logic;
inject_req_i : in std_logic;
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic;
-- keep valid when injecting
inject_clockClass_i : in std_logic_vector(15 downto 0);
inject_port_index_i : in std_logic_vector( 4 downto 0);
inject_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
inject_pck_prio_i : in std_logic_vector( 2 downto 0);
mem_addr_o : out std_logic_vector(9 downto 0);
mem_data_i : in std_logic_vector(17 downto 0);
mem_read_o : out std_logic
rd_ram_data_i : in std_logic_vector(17 downto 0)
);
end psu_packet_injection;
architecture rtl of psu_packet_injection is
type t_state is (WAIT_IDLE, SOF, DO_INJECT, EOF);
type t_state is (WAIT_IDLE, TX_STATUS, SOF, DO_INJECT, EOF);
alias validData : std_logic is mem_data_i(16);
alias startOfPTP : std_logic is mem_data_i(17);
alias validData : std_logic is rd_ram_data_i(16);
alias clockClass : std_logic is rd_ram_data_i(17);
signal state : t_state;
signal counter : unsigned(8 downto 0);
signal announce_cnt : unsigned(6 downto 0);
signal within_packet : std_logic;
signal select_inject : std_logic;
signal inj_src : t_wrf_source_out;
signal inj_snk : t_wrf_sink_out;
signal inj_stb : std_logic;
signal inject_req_latched : std_logic;
signal inject_done : std_logic; -- ML: indicates that requrested injection was successful
signal cyc_d : std_logic;
signal rd_port_info_addr : std_logic;
signal def_status_reg : t_wrf_status_reg;
signal def_status_reg : t_wrf_status_reg;
signal def_status_word : std_logic_vector(15 downto 0);
signal rtu_rsp_valid : std_logic;
begin -- rtl
snk_o.stall <= '1' when (state = DO_INJECT) else src_i.stall;
inject_done <= '1' when (state = EOF and src_i.stall = '0') else '0';
within_packet <= snk_i.cyc;
def_status_reg.has_smac <= '1';
def_status_reg.has_crc <= '0';
def_status_reg.error <= '0';
def_status_reg.is_hp <= '0';
def_status_word <= f_marshall_wrf_status(def_status_reg);
p_injection_request_ready : process(clk_sys_i)
begin
......@@ -141,111 +154,60 @@ begin -- rtl
if rst_n_i = '0' then
state <= WAIT_IDLE;
select_inject <= '0';
no_template_error <= '0';
inj_src.cyc <= '0';
inj_stb <= '0';
inj_src.we <= '0';
rtu_rsp_valid <= '0';
inj_src.adr <= (others =>'0');
else
case state is
when WAIT_IDLE =>
inj_src.cyc <= '0';
inj_stb <= '0';
inj_src.we <= '0';
no_template_error <= '0';
if(inject_req_i = '1') then --ML: we make sure that we remember the packet_sel_i
-- only when req_i HIGH
counter(8) <= inject_packet_sel_i;
counter(7 downto 0) <= (others => '0');
announce_cnt <= (others => '0');
end if;
if(within_packet = '0' and inject_req_latched = '1' and no_template_error = '0') then
if(within_packet = '0' and inject_req_latched = '1') then
state <= SOF;
select_inject <= '1';
inj_src.cyc <= '1';
rtu_rsp_valid <= '1';
else
select_inject <= '0';
end if;
if (rtu_rsp_valid = '1' and select_inject = '1' and rtu_rsp_ack_i = '1') then
rtu_rsp_valid <= '0';
end if;
when SOF =>
if(src_i.stall = '0') then
inj_src.cyc <= '1';
state <= TX_STATUS;
inj_stb <= '1';
state <= TX_STATUS;
inj_src.adr <= c_WRF_STATUS;
end if;
when TX_STATUS =>
inj_src.adr <= c_WRF_STATUS;
if(inj_src.stall = '0') then
inj_stb <= '1';
state <= DO_INJECT_HEADERS;
if(src_i.stall = '0') then
state <= DO_INJECT;
inj_src.adr <= c_WRF_DATA;
else
inj_stb <= '0';
end if;
when DO_INJECT_HEADERS =>
when DO_INJECT =>
if(inj_src.stall = '0') then
inj_stb <= '1';
counter <= counter + 1;
else
inj_stb <= '0';
end if;
if(first_word = '1' and template_first = '0') then -- ML: first word read
first_word <= '0';
end if;
if(validData = '1' and startOfPTP = '1') then
announce_cnt <= announce_cnt + 1;
state <= DO_INJECT_START_PTP
rd_port_info_addr <= '1';
end if;
when DO_INJECT_START_PTP =>
if(inj_src.stall = '0') then
if(src_i.stall = '0') then
inj_stb <= '1';
announce_cnt <= announce_cnt + 1;
counter <= counter + 1;
else
inj_stb <= '0';
end if;
if(announce_cnt = 4) then
state <= DO_INJECT_PORT_STUFF;
end if;
when DO_INJECT_PORT_STUFF =>
if(inj_src.stall = '0') then
inj_stb <= '1';
rd_port_info_addr <= '1';
announce_cnt <= announce_cnt + 1;
counter <= counter + 1;
else
inj_stb <= '0';
end if;
if(announce_cnt = 6) then
state <= DO_INJECT_REST;
end if;
when DO_INJECT_REST =>
if(inj_src.stall = '0') then
inj_stb <= '1';
counter <= counter + 1;
announce_cnt <= announce_cnt + 1;
else
inj_src.stb <= '0';
end if;
if(inj_stb = '1' and validData = '0') then
inj_stb <= '0';
state <= EOF;
end if;
when EOF =>
inj_src.cyc <= '0';
inj_stb <= '0';
......@@ -258,19 +220,31 @@ begin -- rtl
end if;
end process;
-- the last word cannot be user-defined as we use the user bit to indicate odd size
inj_src.sel(1) <= '1';--template_user when (template_last = '1' and first_word = '0') else '1';
inj_src.sel(1) <= '1';
inj_src.sel(0) <= '1';
inj_src.stb <= inj_stb and validData;
inj_src.dat <= inject_clockClass_i when (inj_src.adr = c_WRF_DATA and
announce_cnt = 19) else
f_marshall_wrf_status(def_status_reg)when (inj_src.adr = c_WRF_STATUS) else
mem_data_i(15 downto 0) ;
inj_src.stb <= '1' when (inj_stb = '1' and validData = '1') else '0';
inj_src.dat <= inject_clockClass_i when (inj_src.adr = c_WRF_DATA and clockClass = '1') else
def_status_word when (inj_src.adr = c_WRF_STATUS) else
rd_ram_data_i(15 downto 0) ;
src_o <= inj_src when select_inject = '1' else snk_i;
snk_o <= inj_src when select_inject = '1' else src_i;
mem_addr_o <= '1' & "000" & inject_port_index_i when (announce_cnt = 3 or announce_cnt = 4) else
'0' & std_logic_vector(counter);
mem_read_o <= '0' when (state = WAIT_IDLE) else '1';
inject_done <= '1' when (state = EOF and src_i.stall = '0') else '0';
within_packet <= snk_i.cyc;
inj_snk.ack <= '0';
inj_snk.stall <= '1' when select_inject = '1' else src_i.stall;
inj_snk.err <= '0';
inj_snk.rty <= '0';
src_o <= inj_src when select_inject = '1' else snk_i;
snk_o <= inj_snk when select_inject = '1' else src_i;
rtu_dst_port_mask_o <= inject_port_mask_i when select_inject = '1' else rtu_dst_port_mask_i;
rtu_prio_o <= inject_pck_prio_i when select_inject = '1' else rtu_prio_i;
rtu_drop_o <= '0' when select_inject = '1' else rtu_drop_i;
rtu_rsp_valid_o <= rtu_rsp_valid when select_inject = '1' else rtu_rsp_valid_i;
rtu_rsp_ack_o <= rtu_rsp_ack_i;
-- mem_addr_o <= '1' & "000" & inject_port_index_i when (announce_cnt = 3 or announce_cnt = 4) else
-- '0' & std_logic_vector(counter);
-- mem_read_o <= '0' when (state = WAIT_IDLE) else '1';
end rtl;
modules/wrsw_psu/psu_pkg.vhd
View file @ 5535f4f3
......@@ -45,6 +45,7 @@ use ieee.math_real.log2;
library work;
use work.wr_fabric_pkg.all;
use work.psu_wbgen2_pkg.all;
package psu_pkg is
......@@ -59,10 +60,14 @@ package psu_pkg is
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
rtu_dst_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
snoop_ports_mask_i : in std_logic_vector(g_port_number-1 downto 0);
clock_class_i : in std_logic_vector(15 downto 0);
holdover_on_i : in std_logic;
holdover_clk_class_i : in std_logic_vector(15 downto 0);
detected_announce_o : out std_logic;
srcdst_port_mask_o : out std_logic_vector(g_port_number-1 downto 0);
sourcePortID_match_o : out std_logic;
......@@ -78,23 +83,71 @@ package psu_pkg is
rd_ram_sel_o : out std_logic);
end component;
component psu_packet_injection is
generic(
g_port_number : integer:=18
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
rtu_dst_port_mask_o : out std_logic_vector(g_port_number-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
rtu_dst_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
rtu_prio_i : in std_logic_vector(2 downto 0);
rtu_drop_i : in std_logic;
rtu_rsp_valid_i : in std_logic;
rtu_rsp_ack_o : out std_logic;
inject_req_i : in std_logic;
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic;
inject_clockClass_i : in std_logic_vector(15 downto 0);
inject_port_index_i : in std_logic_vector( 4 downto 0);
mem_addr_o : out std_logic_vector(9 downto 0);
mem_data_i : in std_logic_vector(17 downto 0);
mem_read_o : out std_logic);
inject_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
inject_pck_prio_i : in std_logic_vector( 2 downto 0);
rd_ram_data_i : in std_logic_vector(17 downto 0)
);
end component;
component psu_tx_ctrl is
generic(
g_port_number : integer := 18);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
inject_req_o : out std_logic;
inject_ready_i : in std_logic;
inject_port_mask_o : out std_logic_vector(g_port_number-1 downto 0);
tx_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
tx_ann_detect_mask_i : in std_logic_vector(g_port_number-1 downto 0);
holdover_on_i : in std_logic);
end component;
component psu_wishbone_controller is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_psu_in_registers;
regs_o : out t_psu_out_registers
);
end component;
end psu_pkg;
package body psu_pkg is
......
modules/wrsw_psu/wbgen2_pkg.vhd → modules/wrsw_psu/psu_wbgen2_pkg.vhd
View file @ 5535f4f3
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR PTP Support Unit Controller
---------------------------------------------------------------------------------------
-- File : wbgen2_pkg.vhd
-- File : psu_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from psu_wishbone_controller.wb
-- Created : Sat Mar 21 20:51:34 2015
-- Created : Sun Mar 22 18:54:14 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE psu_wishbone_controller.wb
......@@ -20,9 +20,11 @@ package psu_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_psu_in_registers is record
ptd_tx_ram_rd_dat_i : std_logic_vector(17 downto 0);
end record;
constant c_psu_in_registers_init_value: t_psu_in_registers := (
ptd_tx_ram_rd_dat_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -30,19 +32,25 @@ package psu_wbgen2_pkg is
type t_psu_out_registers is record
pcr_psu_ena_o : std_logic;
pcr_ignore_rx_pid_o : std_logic;
pcr_inj_prio_o : std_logic_vector(2 downto 0);
pcr_holdover_clk_class_o : std_logic_vector(15 downto 0);
rxpm_port_mask_o : std_logic_vector(31 downto 0);
txpm_port_mask_o : std_logic_vector(31 downto 0);
ptd_tx_ann_trig_o : std_logic;
ptd_dbg_holdover_on_o : std_logic;
ptd_tx_ram_rd_ena_o : std_logic;
ptd_tx_ram_rd_adr_o : std_logic_vector(9 downto 0);
end record;
constant c_psu_out_registers_init_value: t_psu_out_registers := (
pcr_psu_ena_o => '0',
pcr_ignore_rx_pid_o => '0',
pcr_holdover_clk_class_o => x"0007",
pcr_inj_prio_o => (others => '0'),
pcr_holdover_clk_class_o => (others => '0'),
rxpm_port_mask_o => (others => '0'),
txpm_port_mask_o => (others => '0'),
ptd_tx_ann_trig_o => '0'
ptd_dbg_holdover_on_o => '0',
ptd_tx_ram_rd_ena_o => '0',
ptd_tx_ram_rd_adr_o => (others => '0')
);
function "or" (left, right: t_psu_in_registers) return t_psu_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -73,6 +81,7 @@ end function;
function "or" (left, right: t_psu_in_registers) return t_psu_in_registers is
variable tmp: t_psu_in_registers;
begin
tmp.ptd_tx_ram_rd_dat_i := f_x_to_zero(left.ptd_tx_ram_rd_dat_i) or f_x_to_zero(right.ptd_tx_ram_rd_dat_i);
return tmp;
end function;
end package body;
modules/wrsw_psu/psu_wishbone_controller.vhd
View file @ 5535f4f3
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : psu_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from psu_wishbone_controller.wb
-- Created : Sat Mar 21 20:51:34 2015
-- Created : Sun Mar 22 18:54:14 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE psu_wishbone_controller.wb
......@@ -39,11 +39,13 @@ architecture syn of psu_wishbone_controller is
signal psu_pcr_psu_ena_int : std_logic ;
signal psu_pcr_ignore_rx_pid_int : std_logic ;
signal psu_pcr_inj_prio_int : std_logic_vector(2 downto 0);
signal psu_pcr_holdover_clk_class_int : std_logic_vector(15 downto 0);
signal psu_rxpm_port_mask_int : std_logic_vector(31 downto 0);
signal psu_txpm_port_mask_int : std_logic_vector(31 downto 0);
signal psu_ptd_tx_ann_trig_dly0 : std_logic ;
signal psu_ptd_tx_ann_trig_int : std_logic ;
signal psu_ptd_dbg_holdover_on_int : std_logic ;
signal psu_ptd_tx_ram_rd_ena_int : std_logic ;
signal psu_ptd_tx_ram_rd_adr_int : std_logic_vector(9 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -73,17 +75,19 @@ begin
rddata_reg <= "00000000000000000000000000000000";
psu_pcr_psu_ena_int <= '0';
psu_pcr_ignore_rx_pid_int <= '0';
psu_pcr_inj_prio_int <= "000";
psu_pcr_holdover_clk_class_int <= "0000000000000000";
psu_rxpm_port_mask_int <= "00000000000000000000000000000000";
psu_txpm_port_mask_int <= "00000000000000000000000000000000";
psu_ptd_tx_ann_trig_int <= '0';
psu_ptd_dbg_holdover_on_int <= '0';
psu_ptd_tx_ram_rd_ena_int <= '0';
psu_ptd_tx_ram_rd_adr_int <= "0000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
psu_ptd_tx_ann_trig_int <= '0';
ack_in_progress <= '0';
else
end if;
......@@ -94,10 +98,12 @@ begin
if (wb_we_i = '1') then
psu_pcr_psu_ena_int <= wrdata_reg(0);
psu_pcr_ignore_rx_pid_int <= wrdata_reg(1);
psu_pcr_inj_prio_int <= wrdata_reg(10 downto 8);
psu_pcr_holdover_clk_class_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(0) <= psu_pcr_psu_ena_int;
rddata_reg(1) <= psu_pcr_ignore_rx_pid_int;
rddata_reg(10 downto 8) <= psu_pcr_inj_prio_int;
rddata_reg(31 downto 16) <= psu_pcr_holdover_clk_class_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -105,9 +111,6 @@ begin
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
......@@ -131,42 +134,17 @@ begin
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
psu_ptd_tx_ann_trig_int <= wrdata_reg(0);
psu_ptd_dbg_holdover_on_int <= wrdata_reg(0);
psu_ptd_tx_ram_rd_ena_int <= wrdata_reg(1);
psu_ptd_tx_ram_rd_adr_int <= wrdata_reg(13 downto 4);
end if;
rddata_reg(0) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(0) <= psu_ptd_dbg_holdover_on_int;
rddata_reg(1) <= psu_ptd_tx_ram_rd_ena_int;
rddata_reg(13 downto 4) <= psu_ptd_tx_ram_rd_adr_int;
rddata_reg(31 downto 14) <= regs_i.ptd_tx_ram_rd_dat_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
......@@ -185,25 +163,21 @@ begin
regs_o.pcr_psu_ena_o <= psu_pcr_psu_ena_int;
-- Ignore rx clockIdentity
regs_o.pcr_ignore_rx_pid_o <= psu_pcr_ignore_rx_pid_int;
-- Inject Packet Priority
regs_o.pcr_inj_prio_o <= psu_pcr_inj_prio_int;
-- Holdover clockClass
regs_o.pcr_holdover_clk_class_o <= psu_pcr_holdover_clk_class_int;
-- Port Mask
regs_o.rxpm_port_mask_o <= psu_rxpm_port_mask_int;
-- Port Mask
regs_o.txpm_port_mask_o <= psu_txpm_port_mask_int;
-- Trig Annouce tx
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
psu_ptd_tx_ann_trig_dly0 <= '0';
regs_o.ptd_tx_ann_trig_o <= '0';
elsif rising_edge(clk_sys_i) then
psu_ptd_tx_ann_trig_dly0 <= psu_ptd_tx_ann_trig_int;
regs_o.ptd_tx_ann_trig_o <= psu_ptd_tx_ann_trig_int and (not psu_ptd_tx_ann_trig_dly0);
end if;
end process;
-- Holdover ON
regs_o.ptd_dbg_holdover_on_o <= psu_ptd_dbg_holdover_on_int;
-- Tx inject/snoop RAM read enable
regs_o.ptd_tx_ram_rd_ena_o <= psu_ptd_tx_ram_rd_ena_int;
-- Tx inject/snoop RAM ADR
regs_o.ptd_tx_ram_rd_adr_o <= psu_ptd_tx_ram_rd_adr_int;
-- Tx inject/snoop RAM DAT
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wrsw_psu/psu_wishbone_controller.wb
View file @ 5535f4f3
......@@ -68,6 +68,16 @@ peripheral {
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Inject Packet Priority";
description = "The priority provided to RTU with which the injected Announce is sent (does not change priority in the Ethernet frame, might not have at all) but affects priority in output queue of SWcore";
prefix = "INJ_PRIO";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 3;
align= 8;
};
field {
name = "Holdover clockClass";
description = "ClockClass to be sent when HW-generating Announce and the one we detect when snooping received Announce";
......@@ -77,7 +87,8 @@ peripheral {
type = SLV;
size = 16;
align= 16;
};
};
};
reg {
......@@ -116,10 +127,40 @@ peripheral {
description = "Some debugging and control for testing";
field {
name = "Trig Annouce tx";
description = "Setting this bit causes PSU to generate Announces as if they were triggered by SoftPLL";
prefix = "TX_ANN_TRIG";
type = MONOSTABLE;
name = "Holdover ON";
description = "This tests holdover condition (info from SoftPLL), mainly to trigger Announce sending";
prefix = "DBG_HOLDOVER_ON";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Tx inject/snoop RAM read enable";
description = "Enables reading from WB RAM used for transmission snooping and injections";
prefix = "TX_RAM_RD_ENA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Tx inject/snoop RAM ADR";
description = "Address to read from Tx inject/snoop RAM";
prefix = "TX_RAM_RD_ADR";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
align = 4;
size = 10;
};
field {
name = "Tx inject/snoop RAM DAT";
description = "data to read from Tx inject/snoop RAM";
prefix = "TX_RAM_RD_DAT";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = SLV;
size = 18;
};
};
......
modules/wrsw_psu/xwrsw_psu.vhd
View file @ 5535f4f3
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