Changed rx and tx user clock frequencies.

This removes warning: [Timing 38-316] Clock period '6.400' specified during out-of-context synthesis of instance 'phy_block.phys' at clock pin 'txusrclk2_in[0]' is different from the actual clock period '3.200', this can lead to different synthesis results. More over this configuration matches example design.

Changed rx and tx user clock frequencies.
This removes warning: [Timing 38-316] Clock period '6.400' specified during out-of-context synthesis of instance 'phy_block.phys' at clock pin 'txusrclk2_in[0]' is different from the actual clock period '3.200', this can lead to different synthesis results. More over this configuration matches example design.
6595de29 · Marek Gumiński · 01b236f8 · 6595de29
Commit 6595de29 authored Sep 13, 2019 by Marek Gumiński
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scb_top_synthesis.vhd top/scb_18ports/scb_top_synthesis.vhd +2 -2

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--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -667,7 +667,7 @@ begin
      CEMASK  => '0',
      CLR     => '0',
      CLRMASK => '0',
-      DIV     => "000",
+      DIV     => "001",
      I       => rxoutclks(i),
      O       => rxusrclk2(i)
      );
@@ -680,7 +680,7 @@ begin
      CEMASK  => '0',
      CLR     => '0',
      CLRMASK => '0',
-      DIV     => "000",
+      DIV     => "001",
      I       => txoutclks(i),
      O       => txusrclk2(i)
      );