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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 7d8e0eba authored by Marek Gumiński's avatar Marek Gumiński
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Some fixes in in synthesis top module

parent d93adeb8
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Showing with 6 additions and 6 deletions
top/scb_18ports/scb_top_synthesis.vhd
View file @ 7d8e0eba
......@@ -252,8 +252,8 @@ architecture Behavioral of scb_top_synthesis is
end component;
signal to_phys : t_phyif_output_array(c_NUM_PHYS-1 downto 0);
signal from_phys : t_phyif_input_array(c_NUM_PHYS-1 downto 0);
signal to_phys : t_phyiftmp_output_array(c_NUM_PHYS-1 downto 0);
signal from_phys : t_phyiftmp_input_array(c_NUM_PHYS-1 downto 0);
signal clk_aux : std_logic;
......@@ -333,8 +333,8 @@ architecture Behavioral of scb_top_synthesis is
clk_sel_o : out std_logic;
uart_sel_o : out std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
phys_o : out t_phyiftmp_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyiftmp_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
......@@ -689,8 +689,8 @@ begin
phys: entity work.transceivers_10gb
port map(
gtwiz_userclk_tx_active_in(0) => '1',
gtwiz_userclk_rx_active_in(0) => '1',
gtwiz_userclk_tx_active_in => (others =>'1'),
gtwiz_userclk_rx_active_in => (others =>'1'),
gtwiz_buffbypass_tx_reset_in => (others => c25m_to_phys_rst),
gtwiz_buffbypass_tx_start_user_in => (others => '0'),
gtwiz_buffbypass_tx_done_out => open,
......
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