Skip to content

R
Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit ecc68af2 authored by Marek Gumiński's avatar Marek Gumiński
Browse files
Options

Changed record types in endpoint.

parent 500d1f1a
Hide whitespace changes
Inline Side-by-side
Showing with 48 additions and 42 deletions
ip_cores/wr-cores-local/modules/fabric/wr_fabric_pkg.vhd
View file @ ecc68af2
......@@ -91,15 +91,21 @@ package wr_fabric_pkg is
end record;
subtype t_wrf_sink_in is t_wrf_source_out;
subtype t_wrf_sink16_in is t_wrf_source16_out;
subtype t_wrf_sink_out is t_wrf_source_in;
subtype t_wrf_sink16_in is t_wrf_source16_out;
subtype t_wrf_sink16_out is t_wrf_source_in;
subtype t_wrf_source16_in is t_wrf_sink16_out;
type t_wrf_source_in_array is array (natural range <>) of t_wrf_source_in;
type t_wrf_source_out_array is array (natural range <>) of t_wrf_source_out;
type t_wrf_source16_out_array is array (natural range <>) of t_wrf_source16_out;
type t_wrf_source16_in_array is array (natural range <>) of t_wrf_source16_in;
subtype t_wrf_sink_in_array is t_wrf_source_out_array;
subtype t_wrf_sink_out_array is t_wrf_source_in_array;
subtype t_wrf_sink16_in_array is t_wrf_source16_out_array;
subtype t_wrf_sink16_out_array is t_wrf_source16_in_array;
function f_marshall_wrf_status (stat : t_wrf_status_reg) return std_logic_vector;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
......
ip_cores/wr-cores-local/modules/wr_endpoint/endpoint_pkg.vhd
View file @ ecc68af2
......@@ -238,10 +238,10 @@ package endpoint_pkg is
gmii_rxd_i : in std_logic_vector(7 downto 0) := x"00";
gmii_rx_er_i : in std_logic := '0';
gmii_rx_dv_i : in std_logic := '0';
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
src_o : out t_wrf_source16_out;
src_i : in t_wrf_source16_in;
snk_o : out t_wrf_sink16_out;
snk_i : in t_wrf_sink16_in;
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
txtsu_ts_value_o : out std_logic_vector(28 + 4 - 1 downto 0);
......
ip_cores/wr-cores-local/modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ ecc68af2
......@@ -372,8 +372,8 @@ package endpoint_private_pkg is
src_dreq_i : in std_logic;
pcs_busy_i : in std_logic;
pcs_error_i : in std_logic;
wb_snk_i : in t_wrf_sink_in;
wb_snk_o : out t_wrf_sink_out;
wb_snk_i : in t_wrf_sink16_in;
wb_snk_o : out t_wrf_sink16_out;
fc_pause_req_i : in std_logic;
fc_pause_delay_i : in std_logic_vector(15 downto 0);
fc_pause_ready_o : out std_logic;
......@@ -628,8 +628,8 @@ package endpoint_private_pkg is
stop_traffic_i : in std_logic := '0';
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
src_wb_i : in t_wrf_source_in;
src_wb_o : out t_wrf_source_out);
src_wb_i : in t_wrf_source16_in;
src_wb_o : out t_wrf_source16_out);
end component;
component ep_rx_status_reg_insert
......@@ -685,8 +685,8 @@ package endpoint_private_pkg is
pcs_fab_i : in t_ep_internal_fabric;
pcs_fifo_almostfull_o : out std_logic;
pcs_busy_i : in std_logic;
src_wb_o : out t_wrf_source_out;
src_wb_i : in t_wrf_source_in;
src_wb_o : out t_wrf_source16_out;
src_wb_i : in t_wrf_source16_in;
fc_pause_p_o : out std_logic;
fc_pause_quanta_o : out std_logic_vector(15 downto 0);
fc_pause_prio_mask_o : out std_logic_vector(7 downto 0);
......@@ -719,8 +719,8 @@ package endpoint_private_pkg is
pcs_error_i : in std_logic;
pcs_busy_i : in std_logic;
pcs_dreq_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink16_in;
snk_o : out t_wrf_sink16_out;
fc_pause_req_i : in std_logic;
fc_pause_delay_i : in std_logic_vector(15 downto 0);
fc_pause_ready_o : out std_logic;
......
ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_path.vhd
View file @ ecc68af2
......@@ -68,7 +68,7 @@ entity ep_rx_path is
g_with_rx_buffer : boolean := true;
g_with_early_match : boolean := false;
g_rx_buffer_size : integer := 1024;
g_use_new_crc : boolean := false);
g_use_new_crc : boolean := false);
port (
clk_sys_i : in std_logic;
clk_rx_i : in std_logic;
......@@ -83,8 +83,8 @@ entity ep_rx_path is
pcs_busy_i : in std_logic;
-- Wishbone I/O
src_wb_o : out t_wrf_source_out;
src_wb_i : in t_wrf_source_in;
src_wb_o : out t_wrf_source16_out;
src_wb_i : in t_wrf_source16_in;
-- flow control signals
fc_pause_p_o : out std_logic;
......@@ -145,7 +145,7 @@ architecture behavioral of ep_rx_path is
signal rxbuf_full : std_logic;
signal rxbuf_dropped : std_logic;
signal src_wb_out : t_wrf_source_out;
signal src_wb_out : t_wrf_source16_out;
signal src_wb_cyc_d0 : std_logic;
signal rst_n_rx_match_buff : std_logic;
......@@ -300,7 +300,7 @@ begin -- behavioral
U_crc_size_checker : ep_rx_crc_size_check
generic map (
g_use_new_crc => g_use_new_crc)
g_use_new_crc => g_use_new_crc)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
......
ip_cores/wr-cores-local/modules/wr_endpoint/ep_rx_wb_master.vhd
View file @ ecc68af2
......@@ -62,8 +62,8 @@ entity ep_rx_wb_master is
snk_dreq_o : out std_logic;
-- Wishbone I/O (master)
src_wb_i : in t_wrf_source_in;
src_wb_o : out t_wrf_source_out
src_wb_i : in t_wrf_source16_in;
src_wb_o : out t_wrf_source16_out
);
end ep_rx_wb_master;
......@@ -74,7 +74,7 @@ architecture behavioral of ep_rx_wb_master is
signal state : t_state;
signal ack_count : unsigned(3 downto 0);
signal src_out_int : t_wrf_source_out;
signal src_out_int : t_wrf_source16_out;
signal tmp_sel : std_logic;
signal tmp_dat : std_logic_vector(15 downto 0);
......
ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_header_processor.vhd
View file @ ecc68af2
......@@ -75,8 +75,8 @@ entity ep_tx_header_processor is
-- WRF Sink (see WRF specification for the details)
-------------------------------------------------------------------------------
wb_snk_i : in t_wrf_sink_in;
wb_snk_o : out t_wrf_sink_out;
wb_snk_i : in t_wrf_sink16_in;
wb_snk_o : out t_wrf_sink16_out;
-------------------------------------------------------------------------------
-- Flow Control Unit signals
......@@ -162,7 +162,7 @@ architecture behavioral of ep_tx_header_processor is
signal oob_state : t_oob_fsm_state;
signal oob : t_wrf_oob;
signal wb_out : t_wrf_sink_out;
signal wb_out : t_wrf_sink16_out;
signal decoded_status : t_wrf_status_reg;
signal abort_now : std_logic;
......
ip_cores/wr-cores-local/modules/wr_endpoint/ep_tx_path.vhd
View file @ ecc68af2
......@@ -74,8 +74,8 @@ entity ep_tx_path is
-- WRF Sink (see WRF specification for the details)
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink16_in;
snk_o : out t_wrf_sink16_out;
-------------------------------------------------------------------------------
-- Flow Control Unit signals
......
ip_cores/wr-cores-local/modules/wr_endpoint/wr_endpoint.vhd
View file @ ecc68af2
......@@ -287,8 +287,8 @@ entity wr_endpoint is
-------------------------------------------------------------------------------
rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
led_link_o : out std_logic;
led_act_o : out std_logic;
......@@ -399,11 +399,11 @@ architecture syn of wr_endpoint is
signal txfra_enable : std_logic;
signal mdio_addr : std_logic_vector(15 downto 0);
signal sink_in : t_wrf_sink_in;
signal sink_out : t_wrf_sink_out;
signal sink_in : t_wrf_sink16_in;
signal sink_out : t_wrf_sink16_out;
signal src_in : t_wrf_source_in;
signal src_out : t_wrf_source_out;
signal src_in : t_wrf_source16_in;
signal src_out : t_wrf_source16_out;
signal rst_n_rx : std_logic;
......@@ -736,7 +736,7 @@ begin
txts_timestamp_valid_o => txts_timestamp_valid,
txts_o => txts_o, -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o => rxts_o, -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o => rxts_o, -- 2013-Nov-28 peterj added for debugging/calibration
regs_i => regs_fromwb,
regs_o => regs_towb_tsu);
......
ip_cores/wr-cores-local/modules/wr_endpoint/xwr_endpoint.vhd
View file @ ecc68af2
......@@ -66,7 +66,7 @@ entity xwr_endpoint is
g_use_new_rxcrc : boolean := false;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false;
g_ep_idx : integer
g_ep_idx : integer := 1
);
port (
......@@ -146,11 +146,11 @@ entity xwr_endpoint is
-- Wishbone I/O
---------------------------------------------------------------------------
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source16_out;
src_i : in t_wrf_source16_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink16_out;
snk_i : in t_wrf_sink16_in;
-------------------------------------------------------------------------------
-- TX timestamping unit interface
......@@ -261,8 +261,8 @@ entity xwr_endpoint is
-------------------------------------------------------------------------------
rmon_events_o : out std_logic_vector(c_epevents_sz-1 downto 0);
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
txts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o : out std_logic; -- 2013-Nov-28 peterj added for debugging/calibration
led_link_o : out std_logic;
led_act_o : out std_logic;
......@@ -408,8 +408,8 @@ begin
wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall,
rmon_events_o => rmon_events_o,
txts_o => txts_o, -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o => rxts_o, -- 2013-Nov-28 peterj added for debugging/calibration
txts_o => txts_o, -- 2013-Nov-28 peterj added for debugging/calibration
rxts_o => rxts_o, -- 2013-Nov-28 peterj added for debugging/calibration
led_link_o => led_link_o,
led_act_o => led_act_o,
link_up_o => link_up_o,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment