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White Rabbit Switch - Gateware
Commit 026a2192 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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top/scb_8/18: remove fpga_clk_aux, not used anymore

parent f61f00f4
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top/scb_18ports/scb_top_synthesis.ucf
View file @ 026a2192
......@@ -7,9 +7,6 @@ NET "fpga_clk_25mhz_n_i" LOC=K23;
NET "fpga_clk_ref_p_i" LOC=J9;
NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_aux_p_i" LOC=A10;
NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
......@@ -302,12 +299,6 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "fpga_clk_aux_n_i" TNM_NET = fpga_clk_aux_n_i;
TIMESPEC TS_fpga_clk_aux_n_i = PERIOD "fpga_clk_aux_n_i" 5 ns HIGH 50%;
#TIMESPEC TS_fpga_clk_aux_n_i = PERIOD "fpga_clk_aux_n_i" 8 ns HIGH 50%;
NET "fpga_clk_aux_p_i" TNM_NET = fpga_clk_aux_p_i;
TIMESPEC TS_fpga_clk_aux_p_i = PERIOD "fpga_clk_aux_p_i" 5 ns HIGH 50%;
#TIMESPEC TS_fpga_clk_aux_p_i = PERIOD "fpga_clk_aux_p_i" 8 ns HIGH 50%;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
NET "from_phys[0]_rx_clk" TNM="phy_rx_clocks";
NET "from_phys[1]_rx_clk" TNM="phy_rx_clocks";
......@@ -1456,8 +1447,6 @@ TIMESPEC TS_ignore8 = FROM "fpga_clk_ref_p_i" TO "phy_rx_clocks" 20ns DATAPATHON
TIMESPEC TS_ignore9 = FROM "phy_rx_clocks" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore18 = FROM "fpga_clk_dmtd_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore19 = FROM "phy_rx_clocks" TO "fpga_clk_dmtd_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore28 = FROM "fpga_clk_aux_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore29 = FROM "phy_rx_clocks" TO "fpga_clk_aux_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore38 = FROM "fpga_clk_ref_p_i" TO "fpga_clk_dmtd_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore39 = FROM "fpga_clk_dmtd_p_i" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 026a2192
......@@ -70,11 +70,6 @@ entity scb_top_synthesis is
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- 250/10 MHz aux clock for Swcore/rephasing AD9516 in master mode
-- (from the AD9516 PLL output QDRII_200CLK)
fpga_clk_aux_p_i : in std_logic;
fpga_clk_aux_n_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -274,8 +269,6 @@ architecture Behavioral of scb_top_synthesis is
signal clk_gtx8_11 : std_logic;
signal clk_gtx12_15 : std_logic;
signal clk_gtx16_19 : std_logic;
signal clk_aux_unused : std_logic;
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal cpu_nwait_int : std_logic;
......@@ -477,17 +470,6 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_CLK_Sys : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
--O => clk_aux,
O => clk_aux_unused,
I => fpga_clk_aux_p_i,
IB => fpga_clk_aux_n_i);
U_Buf_CLK_DMTD : IBUFGDS
generic map (
DIFF_TERM => true,
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 026a2192
......@@ -7,9 +7,6 @@ NET "fpga_clk_25mhz_n_i" LOC=K23;
NET "fpga_clk_ref_p_i" LOC=J9;
NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_aux_p_i" LOC=A10;
NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
......@@ -297,10 +294,6 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "fpga_clk_aux_n_i" TNM_NET = fpga_clk_aux_n_i;
TIMESPEC TS_fpga_clk_aux_n_i = PERIOD "fpga_clk_aux_n_i" 5 ns HIGH 50%;
NET "fpga_clk_aux_p_i" TNM_NET = fpga_clk_aux_p_i;
TIMESPEC TS_fpga_clk_aux_p_i = PERIOD "fpga_clk_aux_p_i" 5 ns HIGH 50%;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
#NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ 026a2192
......@@ -70,10 +70,6 @@ entity scb_top_synthesis is
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- 250/10 MHz aux clock for Swcore/rephasing AD9516 in master mode
-- (from the AD9516 PLL output QDRII_200CLK)
fpga_clk_aux_p_i : in std_logic;
fpga_clk_aux_n_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
......@@ -278,7 +274,6 @@ architecture Behavioral of scb_top_synthesis is
signal clk_gtx8_11 : std_logic;
signal clk_gtx12_15 : std_logic;
signal clk_gtx16_19 : std_logic;
signal clk_aux_unused : std_logic;
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
......@@ -482,15 +477,6 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_CLK_Sys : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
--O => clk_aux,
O => clk_aux_unused,
I => fpga_clk_aux_p_i,
IB => fpga_clk_aux_n_i);
U_Buf_CLK_DMTD : IBUFGDS
......
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